Earticle

초록

영어

Energy consumption is a major concern in many embedded computing systems. Several studies have shown that cache memories account for about 50% of the total energy consumed in these systems. The performance of a given cache architecture is determined to a large degree by the behavior of the application executing on the architecture. The Desktop systems have to accommodate a very wide range of applications and therefore the cache architecture is usually set by the manufacturer as a best compromise given current applications, technology and cost. Unlike desktop systems, embedded systems are designed to run a small range of well-defined applications. In this paper, we explore the tradeoff between thermal and interconnect energy when allocating tasks in MPSoC and to devlop an efficient system. The experimental results show that the devloped technique can reduce interconnects energy by more than 25% on an average with almost the same peak temperature when compared with prior thermal-balanced solutions.

목차

Abstract
 1. Introduction
 2. Related Work
 3. Problem Statement
 4. Power Management Scheme
 5. Circuit Selection and Fault Detection
 6. Test Under Multiple Voltages
 7. Simulation and Synthesis Results
 8. Conclusion
 References

키워드

저자

• Suresh Kumar. K [ PG Scholar, Knowledge Institute of Technology, Salem, India ]
• Anitha S. [ Assistant Professor, Knowledge Institute of Technology, Salem, India ]
• Gayathiri M. [ Assistant Professor, Knowledge Institute of Technology, Salem, India ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Advanced Science and Technology

• 간기

  월간

• pISSN

  2005-4238

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605