Earticle

초록

영어

In this paper a new non-ideal model of 8-bit Current Mode Successive Approximation Analog-Digital Converter (CM-SAR-ADC) has been proposed, the main blocks of CM SAR ADC are a current sample and hold, a current comparator, SAR logic register and current steering digital to analogue converter (DAC). The model is implemented in Matlab Simulink environment with non ideals factors such as switching noise, clock feed through, charge injection, flicker noise, clock jitter, settling error, and the effect of MOS transistor mismatch in the current sample and hold(S/H) and in the current steering DAC models, the delay time and the current offset are introduced as non-ideal sources to the current comparator model. The comparisons of the simulation results using 8-bits CM SAR ADC with ideal and non-ideal models confirmed the effects of the non ideality sources on the parameters of the ADC.

목차

Abstract
 1. Introduction
 2. The ADC Architecture
 3. Behavioral Model of CM SAR ADC
 4. Building Blocks and Non Idealities Factors in CM SAR ADC
  4.1. The non-idealities of Current Sample and Hold
  4.2. Comparator Model
  4.3. SAR Logic Register
  4.4. 4 to 15 Binary to Thermometer Encoder
  4.5. The Current Steering DAC
 5. Simulation Results
  5.1. Dynamic Performance
  5.2. Static Performance
 6. Conclusion
 References

키워드

저자

• Salah Hanfoug [ Advanced Electronics Laboratory (LEA), University of Batna, Avenue Chahid Boukhlouf, 05000, Batna, Algeria ]
• Nour-Eddine Bouguechal [ Advanced Electronics Laboratory (LEA), University of Batna, Avenue Chahid Boukhlouf, 05000, Batna, Algeria ]
• Samir Barra [ Advanced Electronics Laboratory (LEA), University of Batna, Avenue Chahid Boukhlouf, 05000, Batna, Algeria ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of u- and e- Service, Science and Technology

• 간기

  격월간

• pISSN

  2005-4246

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605