Earticle

초록

영어

As the feature sizes of the manufacturing processes is constantly shrinking, the possibility and demand for more functionality on a single chip goes up. This can lead to many problems,e.g. as the memory access bandwidth through the bus gets too low to cope with the demand, also the electrical performance of the bus gets degraded as the number of modules are increased. Our proposed architecture makes use of a switch fabric structure to eliminate the traditional drawbacks of bus based design.
Scheduler becomes the integral part of the switch which decides the scheduling of the SOC devices. In this paper, we have proposed an area efficient scheduler which saves around 22 - 26% of the total scheduler area on the silicon die. This becomes possible because the arbiter we designed is capable of executing two different steps of Islip algorithm in two different clock cycles. In the first cycle, it acts as a grant arbiter while the next cycle makes it an accept arbiter. The design is modified using the folding concept which is used to reduce the silicon area by time multiplexing many algorithm operations into a single functional unit. Both the design of the scheduler is synthesized using 90nm SAED library using Design Compiler of SYNOPSYS with the design constraint of input delay, output delay and clock skew. The original scheduler occupies around 22206 area unit while the proposed scheduler occupies around 17285 area unit of the total silicon area considering the constraint of input delay, output delay and clock skew. The area includes both cell area (Combinational + NCombinational) and Interconnect area.

목차

Abstract
 1. Folding
 2. Crossbar architecture
 3. The Scheduling Algorithm: i-SLIP
 4. Arbiters
 5. Proposed Arbiter:
 6. Original Scheduler
 7. Programmable Priority Encoder
 8. Proposed PPE
 9. Proposed Scheduler:
 10. Synthesis Results:
 11. Simulation result of folded Scheduler using XILINX ISE:
 12. Conclusion
 References

키워드

저자

• Vilas N. Nitnaware [ Department of Electronics Design Technology, Shri Ramdeobaba K. N. Engg. College, Nagpur, India ]
• Shyam S. Limaye [ Principal, Jhulelal Institute of Technology, Nagpur, India. ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Hybrid Information Technology

• 간기

  격월간

• pISSN

  1738-9968

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605