Earticle

초록

영어

Considerable challenges are encountered when bulk CMOS devices are scaled into the sub-100 nm regime for higher integrated circuit (IC) density and performance. Due to their excellent scalability and better immunity to short channel effects, double-gate (DG) MOSFETs are being easily assessed for CMOS applications beyond the 70 nm of the SIA roadmap. For channel lengths below 100 nm, DG MOSFETs still show considerable threshold voltage roll off and to overcome this effect, different gate engineering techniques can be widely used. In this paper, we investigate the influence of gate engineering on the analog and RF performances of dual material double gate (DM-DG) MOSFETs for system-on-chip applications with high K dielectrics using a 2D device simulator. Equivalent oxide thickness (EOT) of gate oxide can be reduced by the usage of high K dielectric materials. The gate engineering technique used here is the dual metal gate technology. This novel structure shows better immunity to DIBL and improved analog performance like trans conductance generation factor, early voltage, output resistance.

목차

Abstract
 1. Introduction
 2. Device structure and parameters
 3. Simulation results
  3.1. Analog performance
 4. Conclusion
 References

키워드

저자

• NIRMAL [ Department of Electronics and Communication Engineering Karunya University ]
• VIJAYA KUMAR [ Department of Electrical and Electronic Engineering Karunya University ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Advanced Science and Technology

• 간기

  월간

• pISSN

  2005-4238

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605