Earticle

This paper proposes an integrative framework for determining a dominant design in the mobile operation systems. A dominant design has emerged as a de facto standard from traditional industries to ICT. ICT-related industries have been reorganized around the mobile industry in which the mobile operation system can be seen as a strategical keystone. In this paper, we develop a holistic approach for the emergence of a dominant design in the mobile operation systems. Firstly, we combined an integrative framework based on previous research findings with new determinants derived from cases of the mobile operation systems. Secondly, we categorized all determinants according to technological, firm-level and environmental factors within our proposed framework. Finally, we compared this framework to patterns coded from cases which include Android and iOS. This results show that a dominant design is likely to emerge as a result of the interaction of the determinants, not the influence of a single determinant. Furthermore, our proposed framework may extend the existing literature on dominant designs in both researchers and practitioners and provide implications to actors for establishing a competition strategy in the mobile telecommunication ecosystems.

The Logic Built In Self Test (LBIST) technique is substantially applied in chip design in most many semiconductor company in despite of unavoidable overhead like an increase in dimension and time delay occurred as it used. Currently common LBIST software uses the MISR (Multiple Input Shift Register) However, it has many considerations like defining the X-value (Unknown Value), length and number of Scan Chain, Scan Chain and so on for analysis of result occurred in the process. So, to solve these problems, common LBIST software provides the solution method automated. Nevertheless, these problems haven't been solved automatically by Tri-state Bus in logic circuit yet. This paper studies the algorithm that it also suggest algorithm that reduce additional circuits and time delay as matching of pattern about 2-type circuits which are CUT(circuit Under Test) and additional circuits so that the designer can detect the wrong location in CUT: Circuit Under Test.