Earticle

The current and future computer industry is changing from single core CPU to Multicore Processors. The next generation computing systems are focusing on parallel computing to solve the problem in fast and high speed using parallel programming concepts. By running more than one task at the same time with multiple processors concurrently or parallel we can achieve high speed in our computing applications. Here the performance improvement is measured in terms of increase in the number of cores per machine and is analyzed for better optimal work load balance. The parallel computers follow different workload scheduler. In this paper we investigate how to tune the performance of threaded applications with balanced load for each core or processor. The focus here is the process of comparative analysis of single core and multicore systems to run an application program for faster execution time and optimize the scheduler for better performance.

This paper proposes and sketches out a new parallel architecture of transputer-based pyramidal parallel array computer (TPPAC) used to process computationally intensive problems for geometric processing applications such as computer vision, image processing etc. It explores how efficiently the pyramid computer architecture is designed using transputer chips, and poses a new interconnection scheme for TPPAC without using additional transputers.

본 논문에서는 프로세서 중심 컴퓨터 구조에서 개발된 MPI 병렬 프로그램을 수정하지 않고 메모리 중심 컴퓨터 구조에서 더 효율적으로 수행시키는 기술을 제안한다. 본 연구에서 제안하는 기술은 메모리 중심 컴퓨터 구조가 가지는 빠른 대용량 공유 메모리 특징을 이용하여 MPI 표준 라이브러리 함수가 수행하는 네트워크 통신을 통한 느린 데이터 전달을 공유 메모리를 통한 빠른 데이터 전달로 대체하여 효율성을 얻는다. 본 연구에서 제안한 기술은 두 개의 프로그램에 구현되었다. 첫 번째 프로그램은 MC-MPI-LIB라고 불리는 수정된 MPI 라이브러리인데 이는 기존 MPI 표준 라이브러리 함수의 의미를 유지하면서 메모리 중심 컴퓨터 구조에서 더 효율적으로 수행한다. 두 번째 프로그램은 MC-MPI-SIM이라고 불리는 시뮬레이션 프로그램인데 이는 프로세서 중심 컴퓨터 구조 상에서 메모리 중심 컴퓨터 구조의 수행을 시뮬레이션한다. 본 논문에서 제안한 기술은 도커 가상화 상에서 구현된 분산 시스템 환경에서 개발하고 시험하였다. 다수의 MPI 병렬 프로그램을 이용하여 제안한 기술의 성능을 측정한 결과 메모리 중심 컴퓨터 구조에서 더 높은 성능으로 수행 가능함을 보였으며, 특히 통신 오버헤드 비율이 높은 MPI 병렬 프로그램의 경우 매우 높은 성능으로 수행 가능하다는 점을 확인하였다.

In this paper, we present a technique that executes MPI parallel programs, that are developed on processor-centric computer architecture, more efficiently on memory-centric computer architecture without program modification. The technique we present here improves performance by replacing low-speed data communication over the network of MPI library functions with high-speed data communication using the property called fast large shared memory of memory-centric computer architecture. The technique we present in the paper is implemented in two programs. The first program is a modified MPI library called MC-MPI-LIB that runs MPI parallel programs more efficiently on memory-centric computer architecture preserving the semantics of MPI library functions. The second program is a simulation program called MC-MPI-SIM that simulates the performance of memory-centric computer architecture on processor-centric computer architecture. We developed and tested the programs on distributed systems environment deployed on Docker based virtualization. We analyzed the performance of several MPI parallel programs and showed that we achieved better performance on memory-centric computer architecture. Especially we could see very high performance on the MPI parallel programs with high communication overhead.

Studies have suggested that the writing process is a mixture of lowand high-level processing for multiple level decision making, which is performed either during pauses or motor execution. Some studies have found that high-level processing is mostly conducted during pauses, but when high-level processing is performed in parallel with motor execution, it is called parallel processing. The purpose of this study is to examine parallel processing in computer-based L2 writing and to identify types of high-level processing concurrent with typing. This study analyzed keylogging data of the L2 English writing of three different proficiency groups and found that only advanced L2 writers were able to perform parallel processing. The parallel events in L2 writing mainly include two components: linguistic and conceptual processing. Linguistic processing is mostly performed in translating episodes where a writer translates one’s ideas into L2 and evaluates the translation in terms of adequacy and acceptability. Also, advanced L2 writers engage in conceptual processing concurrently with typing, mostly at the ideational and epistemic/rhetorical levels. It is hoped that this study will prompt future studies to investigate the real-time process of writing and provide insights on parallel processing in L2 writing.

We propose a new development for calculating a computer-generated hologram (CGH) through the use of multiple general-purpose graphics processing units (GPGPUs). For optimization of the implementation, CGH parallelization, object point tiling, memory selection for object point, hologram tiling, CGMA (compute to global memory access) ratio by block size, and memory mapping were considered. The proposed CGH was equipped with a digital holographic video system consisting of a camera system for capturing images (object points) and CPU/GPGPU software (S/W) for various image processing activities. The proposed system can generate about 37 full HD holograms per second using about 6K object points.

The machine translation industry’s shift from Statistical Machine Translation (SMT) to Neural Machine Translation (NMT) has recently brought renewed focus on Computer-Assisted Translation (CAT) in translation pedagogy. The purpose of this paper is to propose a CAT tool based on classroom parallel corpora. Trankit, a CAT software prototype the author designed, offers a powerful web-based platform for trainee translators along with a wide range of advanced search options and linguistic information such as concordance lines, syntax trees, and frequency information so that students can make full use of their corpus databases. Section 2 and 3 are literature reviews on parallel corpora and CAT, which are the central concepts forming the theoretical background of the design. Section 4 asserts the necessity of a new CAT tool in relations to these two underlying concepts. Section 5 presents the user interface of the program, exploring applications of CAT in translation training.

Writing process involves constant problem-solving at different discourse levels, which is commonly addressed during pauses. However, studies have found that some high-level problems can be solved in parallel with transcription, cases of which are called as parallel events (Alamargot et al., 2007). The parallel events have been primarily investigated in L1 writing context, and this study aimed to broaden the scope of research to include the L2 writing process and identify individual differences among L2 writers. This study discovered parallel events in writing process of three advanced L2 writers, suggesting that parallel events are not exclusive to L1 writing process. Additionally, this study found that parallel events in L2 writing are largely for lexical refinements, followed by textual and ideational restructuring. The writers showed noticeable individual differences in terms of frequency, prominent functions, and dominant occurrence timing of the parallel events. It is hoped that this study will present a new approach towards the temporal analysis on the L2 writing process and offer a better understanding of individual differences in writing process.

컴퓨터생성홀로그램은 수학적으로 모델링된 광학적인 현상을 컴퓨터로 연산한 것이다. 이때 방대한 량의 연산이 필요하기 때문에 실시간으로 고해상도의 홀로그램을 얻기 위해서는 고속 기법이 필요하다. 본 논문에서는 CGH를 위한 두 가지 병렬화를 제안한다. 첫 번째는 GPU 내에서 CGH 알고리즘을 병렬화하는 것이고, 두 번째는 다수의 GPU를 위한 병렬화이다. 제안한 알고리즘 구조는 CUDA를 이용하여 GTX780 Ti GPU에 구현하였다. 약 10K의 입체 정보를 이용하여 $1,024{\times}1,024$의 컬러 홀로그램을 생성하는데 약 106ms가 소요된다.

Computer-generated hologram (CGH) is to mathematically model optical phenomenon with digital computer. Because it requires huge amount of computational power, a fast and high performance technique is needed. In this paper, we proposed two parallelizations for CGH calculation. The first is to parallelize CGH algorithm in a GPU (general processing unit) and the second is to parallelize multiple GPUs. The proposed algorithm was implemented in GTX780 Ti GPU. It calculates a $1,024{\times}1,024$ hologram with 10K object points for about 24ms.

3D 지도를 이용하여 3D 영상을 처리하는 시스템이 많이 상용화되어 있다. 기존에 3D 지도를 처리하기 위한 방법으로 고성능의 시스템을 이용하였다. 하지만 고성능의 시스템을 사용하여 GIS 시스템을 구현할 경우 가격의 부담이 크다는 문제점이 있다. 또한 일반 시스템에서 3D 지도를 처리하려면 3D 지도의 파일의 크기가 크기 때문에 공간영상을 처리하는데 시간이 오래 걸린다는 단점이 있다. 따라서 본 논문에서는 Linux를 기반으로 3D GIS를 위한 병렬 컴퓨터 시스템을 설계 한다.

대칭이고 큰 희소 행렬(Large Sparse Matrices)에 대한 가장 작거나 또는 가장 큰 고유치(Eigenvalues)들을 구하기 위해서 Lanczos 방법이 많이 이용된다. MP(Message Passing) 병렬 컴퓨터에서 global communications은 계산 속도를 떨어뜨린다. 본 논문에서는 s-step Lanczos 알고리즘을 소개하였으며 이 s-step 방법은 기존의 Lanczos 알고리즘에 의해 생성된 행렬에 유사한 축소 행렬을 생성하며 s-step Lanczos 알고리즘에서 한번의 반복은 기존의 Lanczos 알고리즘의 s 번 반복에 해당한다. s-step 방법은 global communications을 최소화하였으며 기존의 알고리즘에 비해 뛰어난 병렬 성질을 가진다. 알고리즘들은 Cray T3E에서 수행되었으며 그 결과를 볼 수 있다.

The Lanczos algorithm is the most commonly used in approximating a small number of extreme eigenvalues for symmetric large sparse matrices. Global communications in MP(Message Passing) parallel computer decrease the computation speed. In this paper, we introduce the s-step Lanczos method, and s-step method generates reduction matrices which are similar to reduction matrices generated by the standard Lanczos method. One iteration of the s-step Lanczos algorithm corresponds to s iterations of the standard Lanczos algorithm. The s-step method has the minimized global communication and has the superior parallel properties to the standard method. These algorithms are implemented on Cray T3E and performance results are presented.

CFD code that simulates stator-rotor interactions is developed applying parallel computing method. Modified Multi-Block Grid System which enhances perpendicularity in grid and is appropriate in parallel processing is introduced and Patched Algorithm is applied in sliding interface which is caused by movement of rotor. The experimental model in the turbo-machine is composed of 11 stators and 14 rotors. Analyses on two test cases which are one stator - one rotor model and three stators - four rotors model are performed. The results of the two cases have been compared with the experimental test data.

대규모의 업무처리나 복잡한 연산을 요구하는 응용 분야에서는 프로그램의 병렬화를 이용하는 병렬 컴퓨터 시스템이 요구되고 있다. 이 병렬 컴퓨터 시스템의 핵심 작업 중 하나가 동기화이다. 동기화 작업 중 가장 대표적인 방법이 장벽 동기화인데 이 방법은 동기화에 참여하는 모든 프로세서들이 모두 장벽에 도달할 때까지 다음 작업을 진행사킬 수 없게 만드는 것이다. 장벽 동기화는 소프트웨어에 의한 방법, 하드웨어에 의한 방법, 그리고 그 두 가지가 결합된 방법 등이 있는데 이 중에서 하드웨어에 의한 방법이 가장 빠르고 start-up overhead가 적다는 장점으로 인하여 널리 쓰이는 추세이다. 본 논문에서는 하드웨어에 의한 방법 중에서 간단한 오류를 해결할 수 있고 보다 빠른 동기화를 가능하게 하는 새로운 스위치 모듈을 제안한다. 새로운 스위치 모듈과 더불어 제안하는 장벽 동기화는 기존에 제안되었던 방법에 비해서 스위치에 모든 것을 의존하는 방식이 아니라 프로세서에 의해 동작되는 부분이 많기 때문에 적은 하드웨어 비용을 들이고서 효과적인 장벽 동기화를 실행한다. 새로 제안하는 장벽 동기화는 어떠한 망의 구조에서도 구현될 수 있게 설계되었다 . 본 논문에서는 MIN에서의 장벽 동기화에 대한 비교만을 성능 평가하였는데 24.6% - 24.8%의 평균 지연 시간의 감소를 보였다. 하지만 임의의 망인 비정규적인 망에서 보다 나은 성능 향상을 보일 것을 기대한다.

The parallel computer system that uses parallel program on the application such as a large scale business or complex operation is required. One of crucial operation of parallel computer system is synchronization. A representative method of synchronization is barrier synchronization. A barrier forces all process to wait until all the process reach the barrier and then releases all of the processes. There are software schemes, hardware scheme, or combinations of these mechanism to achieve barrier synchronization which tends to use hardware scheme. Besides, barrier synchronization lets parallel computer system fast because it has fewer start-up overhead. In this paper, we propose a new switch module that can implement fast and fault-tolerant barrier synchronization in hardware scheme. A proposed barrier synchronization is operated not in full-switch-driven method but in processor-driven method. An effective barrier synchronization is executed with inexpensive hardware supports. Therefore, a new proposed hardware barrier synchronization is designed that it is operated in arbitrary network topology. In this paper, we only show comparison of barrier synchronization on Multistage Interconnection Network. This research results in 24.6-24.8% reduced average delay. Through this result, we can expect lower average delay in irregular network.

In this paper, we propose a matrix hypercube graph as a new topology for parallel computer and analyze its characteristics of the network parameters, such as degree, routing and diameter. N-dimensional matrix hypercube graph MH(2,n) contains 22n vertices and has relatively lower degree and smaller diameter than well-known hypercube graph. The matrix hypercube graph MH(2,n) and the hypercube graph Q2n have the same number of vertices. In terms of the network cost, defined as the product of the degree and diameter, the former has n2 while the latter has 4n2. In other words, it means that matrix hypercube graph MH(2,n) is better than hypercube graph Q2n with respect to the network cost.

We proposed a XMESH(crossed-mesh) topology as a suitable interconnection for the massively parallel computer architectures, and presented performance analysis of the proposed interconnection topology. Horizontally, the XMESH has the same links as those of the toroidal mesh(TMESH) or toroid, but vertically, it has diagonal cross links instead of the vertical links. It reveals desirable interconnection characteristics for the massively parallel computers as the number of nodes increases, while retaining the same structural advantages of the TMESH such as the symmetric structure, periodic placement of subsystems, and constant degree, which are highly recommended features for VLSI/WSI implementations. Furthermore, n*k XMESH can be easily expanded without increasing the diameter as long as n.leq.k.leq.n+4. Analytical performance evaluations show that the XMESH has a shorter diameter, a shorter mean internode distance, and a higher message completion rate than the TMESH or the diagonal mesh(DMESH). To confirm these results, an optimal self-routing algorithm for the proposed topology is developed and is used to simulate the average delay, the maximum delay, and the throughput in the presence of contention. In all cases, the XMESH is shown to outperform the TMESH and the DMESH regardless of the communication load conditions or the number of nodes of the networks, and can provide an attractive alternative to those networks in implementing massively parallel computers.

With the rapidly increasing complexity of decision-marking or system development in the fields of industry, management, etc., modelling techniques using simulation has become more highlighted. Particularly, the advent of parallel computer systems not only has opened a new horizon of parallel simulation, but also has greatly contributed to the speed-up of the execution of simulation. The implementation of parallel simulation, however, is not a easy job for those who accustomed to the existing computer systems. And it is also necessarily confronted with the problem of synchronization conflict in the process. Thus, how to allow a wider community of users to gain access to parallel simulation while solving synchronization conflicts has become an important issue in simulation study. As a method to solve these problems, this paper is primarily concerned with the implementation of GPSS which is a generally used simulation language for discrete event simulation, onto a parallel computer using C-LINDA. For that, this paper, is to suggest a model and algorithm and to experiment it using a case.

This paper describes the design and test of an on-line non-invasive network performance monitor (hardware portion) for the SPAX parallel computer. The SPAX parallel computer supports up to 256 intel P6 processors with 4 P6 processors constituting a processign node. The nodes are interconnected with a dual two-level crossbar network calle dXcent-net. Since the performance of the SPAX parallel computer is highly dependent on the proper and efficient operation of the network, an on-line non-invasive network performance monitor (with hardware components) has been developed to aid in the monitoring and tunign of the Xcent-net. Successful testing of a prototype node monitor board and PC interface system shows that our monitor design provides a low-cost practical solution to this problem.

In this paper, we present a message transfer scheme for efficient message passing in the hierarchically structured multiprocessor computer SPAX(Scalable Parallel Architecture computer based on X-bar network). The message transfer scheme provides interface not only with operating system but also with end users. In order to transfer two types of control message and data message efficiently, it supports both of memory-mapped transfer and DMA-based transfer. Dual-port RAMs are used as message buffers, and control and status registers provide efficient programming interface. Interlaced parity scheme is adopted for error control. If any error is detected at receiving node, errored packet is resent by sender according to retry mechanism. In conjunction with retry mechanism, watchdog timers are used to protect infinite waiting and repeated retry. The proposed message transfer scheme can be applied to input/output nodes and communication connection nodes as well as processing nodes in the SPAX.

A computer simulation method is introduced to understand the joining phenomena of PC and CFRP by estimating the temperature of the weld zone. Following the prior or preliminary research, the power range was set between 3 watts and 7 watts, and the scanning speed was set at 500 mm/min and 1,000 mm/min, respectively. Based on the computer simulation, the temperature near the joining boundary was not sufficient at the scanning speed of 1,000 mm/min, regardless of the selected powers. However, the temperature increases above the melting temperature of the selected polymers at the scanning speed of 500 mm/min. The simulation results were compared with actual weld samples to validate its actual use.

실생활에서 2개의 병렬형 대기행렬 시스템은 흔히 발견된다. 병렬형 대기행렬 시스템에서 각 작업장은 서로 다른 고객 도착패턴과 고객 서비스 시간 분포를 갖는 경우가 많다. 이 논문은 서로 다른 서비스 시간을 갖는 병렬형 대기행렬 시스템에 총 서버 수가 제한되어 있는 상황에서 각각의 작업장에 적절한 수의 서버를 배치하는 문제를 다룬다. 각 작업장은 제한된 수의 서버를 전체 시스템의 가중평균 시스템 시간이 최소가 되는 기준에 따라 배치 받는다. 일반적으로 M/M/c 시스템은 시스템 시간에 대한 해석적 방법의 산출식이 알려져 있다. M/M/c 시스템에 대한 최적 서버 배치 방안을 해석적 방법에 따라 계산한 결과를 컴퓨터 시뮬레이션 실험 결과와 비교해 본 결과, 두 가지 방법에 의한 최적 해가 동일함이 확인되었다. M/M/c 시스템의 최적화 과정에서 발견한, 각 작업장의 유효작업부하가 가장 비슷하거나 같게 되도록 서버를 배치하는 방식인 CETI 규칙에 따라 M/G/c, G/M/c 그리고 G/G/c 시스템에 대한 컴퓨터 시뮬레이션 실험 결과를 제시하였다. 그 결과, 해석적 방법으로는 증명할 수 없지만 일부 G/G/c 시스템을 제외한 나머지 경우에서는 CETI 규칙이 최적의 서버 배치 방식인 것으로 나타났다.

A queueing system with 2 parallel workstations is common in the field. Typically, the workstations have different features in terms of the inter arrival times of customers and the service times for the customers. Computer simulation study on the optimal server allocation for parallel heterogeneous queueing systems with fixed number of identical servers is presented in this paper. The queueing system is optimized with respect to minimizing the weighted system time of the customers served by 2 parallel workstations. The system time formula for the M/M/c systems in Kendall's notation is known. Thus, we first compute the optimal allocation for parallel M/M/c systems, comparing the results with those from the computer simulation experiments, and have the same results. The CETI rule is devised through optimizing M/M/c cases, which allocates the servers based on Close or Equal Traffic Intensities between workstations. Traffic intensity is defined as the arrival rate divided by the service rate times the number of servers. The CETI rule is shown to work for M/G/c, G/M/c queueing systems by numerous computer simulation experiments, even if the rule cannot be proven analytically. However, the CETI rule is shown not to work for some of G/G/c systems.