Earticle

The air logistics process is complex and needs many informations because various agencies participate in the logistics service and many stakeholders in air logistics. But it is hard to improve the infra of facilities because of an enormous expense, so air logistics process has to simplify for growing air freight. Nevertheless some documents are same, they should be changed due to different format. Also documents have to change even though different documents have same informations. Consequently, errors are increased because the names of the same data are different from each other and stakeholders have to reproduce the documents. In order to mitigate these problems, we selected documents and analyzed document data for the interface optimization in general air logistics process. Next, we unified the data names and defined contents of data. Also we set the type of the defined data on DB type, and gave the code to the defined data. It made easy to exchange informations among the stakeholders to match documents corresponding with the defined data. Finally, the simulation of air logistics processes was performed the quantitative analysis of the data that occur in the air logistics. In conclusion, we expect to reduce the inefficiency such as reproduction of data and the errors by improving the interface of information.

The air logistics process is complex and need many informations because various agencies participate in the logistics service and there are many stakeholders in air logistics. But it is hard to improve the infra of facilities because of an enormous expense, so it needs to simplify air logistics process for growing air freight. When documents are sent, it needs to change the form of documents in spite of same document due to different form by agencies. Also documents are changed even though different documents have same informations. Consequently, errors are increased because the names of the same data are different from each other and stakeholders reproduce the documents. In order to mitigate these problems, we selected documents and analyzed data of documents for the interface optimization in general air logistics process. Next, we unified the names of data and defined contents of data. Also we set the type of the defined data on DB type, and gave the code to the defined data. It made easy to exchange informations among the stakeholders to match documents corresponding with the defined data.

Particle swarm optimization (PSO) is employed to train fuzzy-neural networks (FNN), which can be employed as an important building block in real life robot systems, controlled by voice-based commands. The FNN is also trained to capture the user spoken directive in the context of the present performance of the robot system. The system has been successfully employed in a real life situation for navigation of a mobile robot.

철도 현장 데이터를 기반으로 실시간으로 철도 사고 위험을 예측·예방하는 실시간 철도 안전 통합 감시제어시스템은 네트워크 통신으로 연결된 복수의 내부 시스템으로 구성되어 있다. 본 논문에서는 이들 내부 시스템간의 통신 인터페이스를 분석하고, 시스템 동작 시 취약 요소가 될 가능성이 있는 1) 열차 상태 데이터의 무선전송, 2) DDS(Data Distribution Service) 통신에서의 데이터 전송 단위(Topic) 설계, 3) WAN 상에서의 DDS 통신성능에 대하여 실험을 통하여 최적화 방안을 도출하여, 이를 토대로 실시간적인 철도 안전을 위한 감시 및 제어에 적합한 통신 인터페이스를 설계하였다.

A real-time integrated railwa\y safety monitoring and control system that predicts and prevents real-time railway accidents based on railway on-site data is composed of a plurality of internal systems connected by network communication. In this paper, we analyze the communication interface between internal systems, and perform experiments to examine the weak points of communication. Those experiments are about 1) wireless data transmission of train status, 2) topic design for DDS communication, and 3) DDS communication performance on WAN. Based on experiment results, we design a suitable communication interface for real-time monitoring and control for railway safety.

본 연구는 도시철도 무인운전시스템 차륜-레일 인터페이스에 대한 연구로써 용인경전철과 비슷한 완전자동 무인운전시스템으로 운영 중인 미국 JFK ART 시스템에서 사용되고 있는 철제차륜 차량 및 레일 조건을 기반으로 하여 용인경량전철 시스템에 적용하기 위한 차륜-레일 인터페이스에 대한 고찰을 통해 해외 무인운전시스템 도시철도차량의 국내 도입 시에 철도차량의 안정적인 운행을 위한 차륜-레일간의 인터페이스 최적화 방안을 제시 하였다.

This is study on the wheel-rail interface and track condition proposed for YongIn Light Rail Transit. Based on the conditions of steel wheeled vehicles and rails used in the US JFK ART system, which is operated in almost the same system as YongIn Light Rail, the Yongin Light Rail System Optimization methods for the rail gauges used in this study were considered, and through verification, it was confirmed that normal operation was possible even with new and worn wheels.

The concept of energy-efficient networking has begun to spread in the past few years, gaining increasing popularity. A common opinion among networking researchers is that the sole introduction of low consumption silicon technologies may not be enough to effectively curb energy requirements. Thus, for disruptively boosting the network energy efficiency, these hardware enhancements must be integrated with ad-hoc mechanisms that explicitly manage energy saving, by exploiting network-specific features. The IEEE 802.3az Energy Efficient Ethernet (EEE) standard is one of such efforts. EEE introduces a low power mode for the most common Ethernet physical layer standards and is expected to provide large energy savings. However, it has been shown that EEE may not achieve good energy efficiency because mode transition overheads can be significant, leading to almost full energy consumption even at low utilization levels. Coalescing techniques such as packet coalescing and interrupt coalescing were proposed to improve energy efficiency of EEE, but their implementations typically adopt a simple policy that employs a few fixed values for coalescing parameters, thus it is difficult to achieve optimal energy efficiency. The paper proposes adaptive interrupt coalescing (AIC) that adopts an optimal policy that could not only improve energy efficiency but support performance. AIC has been implemented at the sender side with the Intel 82579 network interface card (NIC) and e1000e Linux device driver. The experiments were performed at 100 M bps transfer rate and show that energy efficiency of AIC is improved in most cases despite performance consideration and in the best case can be improved up to 37% compared to that of conventional interrupt coalescing techniques.

It's general a trend to use the load/unload mechanism in the small form factor HDD, like 2.5", 1.8" and 1.0". The load/unload mechanism has tittle opportunity of head/media contact during the disk spin-up and down. However, the load/unload mechanism needs the precise integration technology with slider, suspension ramp, load/unload velocity and so on, and all of these components should be designed simultaneously, not an individually. In this paper, we measured the load/unload velocity in the drive level, and executed the load/unload dynamics with this velocity profiles. We could find the current load/unload mechanism suitable to the long load/unload test.

첨단산업의 발전에 따라 영상처리 하드웨어의 연구는 필수적이고, 실제 칩 동작을 위해서는 게이트 수준의 타이밍 검증이 필요하다. 이를 위해 주로 FPGA 기반 검증이 이루어지는데 기존에는 DDR3 메모리 인터페이스를 적용했지만, 최근에는 FPGA 스펙이 향상되면서 DDR4 메모리가 사용된다. 이 때 기존에 사용하던 메모리 인터페이스를 적용하면 CPU와 메모리의 성능 차이에 의한 신호들의 타이밍 불일치가 발생하기 때문에 사용할 수 없다. 본 논문에서는 기존 인터페이스 시스템 FSM의 State 최적화를 통해 문제를 해결하고, 이 과정에서 AXI Data Width 수정을 통해 데이터 읽기 속도를 2배 증가시킨다. 실제 사례 분석을 위해 Xilinx 사의 SoC보드 중 DDR3 메모리를 사용하는 ZC706과 DDR4 메모리를 사용하는 ZCU106을 사용한다.

With the development of advanced industries, research on image processing hardware is essential, and timing verification at the gate level is required for actual chip operation. For FPGA-based verification, DDR3 memory interface was previously applied. But recently, as the FPGA specification has improved, DDR4 memory is used. In this case, when a previously used memory interface is applied, the timing mismatch of signals may occur and thus cannot be used. This is due to the difference in performance between CPU and memory. In this paper, the problem is solved through state optimization of the existing interface system FSM. In this process, data read speed is doubled through AXI Data Width modification. For actual case analysis, ZC706 using DDR3 memory and ZCU106 using DDR4 memory among Xilinx's SoC boards are used.