Earticle

본 논문에서는 웨어러블 디바이스용 SVGA급(800×600 pixel) Flip-chip 기반의 마이크로 LED 디스플레 이 광원 모듈 연구를 통해 마이크로LED 제작 공정을 개선하고, 시제품의 성능을 측정하여, 제품의 상용화 가능성 을 분석하였다. 먼저, 800×600 Flip-chip 기반 마이크로LED 어레이와 PM 구동 평가를 위해 32×32 어레이를 설 계 및 제작하여, 그 성능 및 제품화의 가능성을 확인하였으며, 제작 공정 기술에서 Self align 전극 형성 기술과 고집적화 어레이의 Mesa 형성을 위한 드라이 에칭 기술을 적용하여 생산성을 향상하였다. 본 연구를 기반으로 추 후 마이크로LED가 제품화시 향후 플렉서블 디스플레이 뿐만이 아닌 다양한 분야에서 적용 가능함으로 관련 산업 으로의 파급효과가 클 것으로 예상된다.

In this paper, we try to analyze the commercial potential of products by improving the micro-LED manufacturing process and measuring the performance of prototypes through research on the SVGA-class (800×600 pixel) flip-chip-based micro LED display light module for wearable devices. First, the 800×600 flip-chip based microLED array and the 32×32 array were designed and manufactured for PM driving evaluation, and their performance and potential for commercialization were confirmed. Productivity was improved by applying dry etching technology to form Mesa. Based on this study, when microLED is commercialized in the future, it is expected to have a large ripple effect on related industries as it can be applied to various fields as well as flexible displays in the future.

Flip Chip 제품 난이도 증가에 따라 신뢰성 관점에서 안정적인 Package (이하 PKG) 소재 기술에 대한 관심이 점차 높아지는 추세이다. 현재 flip chip PKG의 주요 신뢰성 불량은 Sn bridge와 Cu 확산 이다. 위 2가지 형태 모두 본질적으로는 bump 주변 잔류한 flux residue에 의하여 발생한 미세 공극이 유발하는 불량이다. 이러한 형태의 신뢰성 불량 발생 문제점을 최소화하기 위해 Molded Under-Fill (이하 MUF) 소재의 핵심 조성과 flux 간 상관 관계를 검토하였다. 금번 연구를 통하여 MUF 소재의 main 구성 요소인 base resin, filler와 flux에 대한 상관 관계를 정의 하였으며, 이러한 lesson learn을 토대로 flux immunity가 개선된 MUF 소재 조성을 설계할 수 있었다. 현재 해당 소재 조성으로 흡습 신뢰성 85%/85%/24hrs 확보와 파괴 분석으로 bump 주변 미세 공극의 미 발생을 확인 하였다. 본 연구 결과는 양산 단계에서의 flip chip 공정 수율 향상과 MUF와 flux 간 상용성 연구에 대한 이해를 돕는데 기여할 것으로 예상된다.

As the difficulty of flip chip products increase, interest in stable PKG material technology from the viewpoint of reliability is increasing. Currently, the representative of poor reliability that are mainly occurring in flip chip PKG are Sn bridge and Cu dendrite. Two type defects are caused by void generated by the flux residue around the bump. In order to essentially minimize the risk of this type of reliability failure, the linkage between the composition of Molded Under-fill (MUF) and flux, which is related material, was reviewed. In this study, the correlation between base resin and filler, which is the main component of MUF, and flux, was defined, and the material composition design was carried out by refer to lesson learn. With the current material composition, it was confirmed that moisture absorption reliability 85%/85%/24hrs pass result and void did not occur during destructive analysis, and developed MUF has shown flux immunity improving result in flip Chip PKG. We think this study can be used in yield enhancement of flip chip process and give insights to study in compatibility between MUF and flux.

Flip chip 제품의 난이도 증가에 따라 solder wetting 및 신뢰성 관점에서 강점을 갖는 flux 소재에 대한 관심이 높아지고 있다. 지용성 flux의 경우 별도의 세정 공정이 없기 때문에 공정 효율화 측면에서 유리하나, 리플로우 공정이후 반응을 마친 잔여물이 잔존하게 되는 경우 Cu migration 및 delamination을 발생시킬 수 있다. 본 연구에서는 저잔사 flux 구현을 위해 신규 resin에 적합한 solvent 및 activator를 변경 하였으며, package 환경에서 non-wet 및 신뢰성 개선 유무를 확인하였다. 저장 안정성 평가를 통해 신규 소재에 대한 안정성을 확보하였으며, boiling point가 상이한 solvent와 activator 2종 적용 및 activator 함량 증대를 통해 non-wet 미 발생 flux 소재를 확보하였다. 해당 소재에 대한 신뢰성 검증 이후 평면 분석 결과 flux residue 기인성 delamination 현상은 발견되지 않았으며, 이를 통해 저잔사 flux에 대한 최종 조성을 확보하였다.

As the difficulty of flip chip products increases, there is a growing interest in the material of flux, which is safe from the solder wetting and reliability. In the case of no clean flux, there is merit in terms of process efficiency because there is no cleaning process. But Cu migration and delamination can be occurred if the residue remains after the reflow process. In this study, major element materials, solvent and activator, are changed and confirmed effect of non-wet and reliability in the package environment. Stability of materials were secured through storage stability evaluation, and we found out non-wet zero materials through the application of two types of solvent and activator with different boiling point and the increase of activator content. After reliability test, no delamination was found in the plane analysis, which secured the final composition of low residue flux.

Bare-chip packaging becomes more popular along with the miniaturization of IT components. In this paper, we have studied flip-chip process, and developed automated bonding system. Among the several bonding method, NCP bonding is chosen and batch-type equipment is manufactured. The dual optics and vision system aligns the chip with the substrate. The bonding head equipped with temperature and force controllers bonds the chip. The system can be easily modified for other bonding methods such as ACF In bonding process, the bonding forte and temperature are known as the most dominant bonding parameters. A parametric study is performed for these two parameters. For the test sample, we used standard flip-chip test kit which consists of FR4 boards and dummy flip-chips. The bonding test was performed fur two types of flip-chips with different chip size and lead pitch. The bonding temperatures are chosen between $25^{\circ}C\;to\;300^{\circ}C$. The bonding forces are chosen between 5N and 300N. The bonding strength is checked using bonding force tester. After the bonding force test, the samples are examined by microscope to determine the failure mode. The relations between the bonding strength and the bonding parameters are analyzed and compared with bonding models. Finally, the most suitable bonding condition is suggested in terms of temperature and force.

본 연구에서는 Ag anisotropic conductive adhesive(ACA)의 종류, 경화 조건 및 안테나 패턴의 재질에 따른 flip chip bonding된 RFID die의 접합부 신뢰성이 조사되었다. 접합강도 측정에 의하여 접합강도가 최적화되는 공정 시간을 결정할 수 있었으며, 그러한 최적의 공정조건에서는 paste-type Ag ink로 인쇄된 안테나 상에서의 RFID die의 접합강도가 Cu 재질 안테나에 비해 상대적으로 높게 측정됨을 알 수 있었다. RFID tag의 인식거리 측정 시험을 통하여 적절한 경화 조건이 적용된다면 안테나의 재질이 인식거리 변화에 가장 주요한 영향을 미치는 인자임을 알 수 있었다. 아울러 Cu 안테나 패턴은 RFID die의 접합 과정에서 곡률을 가지며 휘어지면서 인식거리와 관련된 long-tem reliability를 악화시킬 수 있음을 관찰할 수 있었다.

The ball shea. tests for ball grid array (BGA) and flip chip packages were carried out with different displacement rates to find out the optimum condition of the displacement rate for this test. The BGA packages consisted of two different kinds of solder balls (eutectic Sn-37wt.%Pb and Sn-3.5wt.%Ag) and electroplated Au/Ni/Cu substrate, whereas the flip chip package consisted of electroplated Sn-37Pb solder and Cu UBM. The packages were reflowed up to 10 times, or aged at 443 K up to 21 days. The variation of the displacement rate resulted in the variations of the shear properties such as shear force, displacement rate at break, fracture mode and strain rate sensitivity. The increase in the displacement rate led to the increase of the shear force and brittleness of solder joints.

Atmospheric pressure plasma equipment was successfully applied to the flip chip BGA manufacturing process to improve the uniformity of flux printing process. The problem was characterized as shrinkage of the printed flux layer due to insufficient surface energy of the flip chip BGA substrate. To improve the hydrophilic characteristics of the flip chip BGA substrate, remote DBD type atmospheric pressure plasma equipment was developed and adapted to the flux print process. The equipment enhanced the surface energy of the substrate to reasonable level and made the flux be distributed over the entire flip chip BGA substrate uniformly. This research was the first adaptation of the atmospheric pressure plasma equipment to the flip chip BGA manufacturing process and a lot of possible applications are supposed to be extended to other PCB manufacturing processes such as organic cleaning, etc.

A flip-chip bonding system using IR laser with a wavelength of 1064 nm was developed and associated process parameters were analyzed using Taguchi methods. An infrared laser beam is designed to transmit through a silicon chip and used for transferring laser energy directly to micro-bumps. This process has several advantages: minimized heat affect zone, fast bonding and good reliability in the microchip bonding interface. Approximately 50 % of the irradiated energy can be directly used for bonding the solder bumps with a few seconds of bonding time. A flip-chip with 120 solder bumps was used for this experiment and the composition of the solder bump was Sn3.0Ag0.5Cu. The main processing parameters for IR laser flip-chip bonding were laser power, scanning speed, a spot size and UBM thickness. Taguchi methods were applied for optimizing these four main processing parameters. The optimized bump shape and its shear force were modeled and the experimental results were compared with them. The analysis results indicate that the bump shape and its shear force are dominantly influenced by laser power and scanning speed over a laser spot size. In addition, various effects of processing parameters for IR laser flip-chip bonding are presented and discussed.

Recently many studies being carried out to increase the light efficiency of LED. The external quantum efficiency of LED, generally the light efficiency, is determined by the internal quantum efficiency and the light extraction efficiency. The internal quantum efficiency of LED was already reached to more than 90%, but the light extraction efficiency is still insufficient compared with the internal quantum efficiency because the total internal reflection is generated in the interface between the LED chip and air. Thus, we studied about flip chip LED with PSS and performed the optical simulation which find more optimized PSS for flip chip LED to increase the light extraction efficiency. Decreasing of the total internal reflection and effect of diffused reflection according to PSS improved the light extraction efficiency. To get more higher the efficiency, we simulated flip chip with PSS that the parameters are arrangement, edge spacing, radius, height and shape of PSS.

In this study, thermo-compression(TC) and vacuum reflow(VR) bonding processes of fine pitch interconnection were optimized using Type 7 Sn-3.0Ag-0.5Cu solder paste. A chip with Cu pillar Sn-2.5Ag bumps and BT substrate with ENEPIG surface finish were used, and the thickness and the aperture ratio of the metal mask were 30 ㎛/50 ㎛ and 70%/100%, respectively. As a result of optimizing the printing process, a metal mask with a thickness of 30 ㎛ and an aperture ratio of 100% was selected. As a result of the TC and VR bonding processes optimization, Cu₆Sn₅ and (Cu,Ni)₆Sn₅ IMC layers were formed on the top and bottom of the solder joint, respectively. In the conventional TC process sample, the thickness of the solder was measured to be 4.1 ㎛, and the IMC thickness ratio was calcu- lated to be 40%. Also, in the TC and VR process samples with solder paste, the thickness of the solder was meas- ured to be 6.5 ㎛ and 10.3 ㎛, respectively, and the ratio of the IMC thickness was calculated to be about 32% and 43%. It was expected that it would be beneficial to reliability by reducing the occurrence and propagation of cracks in the solder joint due to the effect of lowering the IMC thickness ratio as the volume of the solder becomes larger than that of the conventional TC process.

The package-on-package technology has been developed to facilitate high-density integration of semiconductor packaging. As the solder bump pitch is decreased, the void content in solder bump joints increases, thereby decreasing its reliability. Consequently, vacuum reflow (VR) is used to increase void fluidity and decrease void content in micro bump joints. Generally, silicon chips in application processor modules are bonded using thermal compression (TC) bonding, followed by the attachment of passive components through hot air reflow soldering. However, the simultaneous bonding of Si chips and passive components using VR can improve productivity. In this study, we performed TC and VR bonding without additional solder pastes, between an Si chip with a Cu pillar/ Sn-2.5Ag bump and a bismaleimide triazine substrate plated with electroless-nickel electroless-palladium immersion- gold. It was observed that the void content at the Si chip solder joints yielded by VR (10.8%) was similar to that yielded by TC (11.2%). Furthermore, the Si chip solder joint of the VR sample was thicker than that of the TC sample. This process also resulted in the formation of the intermetallic compounds Cu6Sn5, (Cu,Ni)6Sn5, Ag3Sn, and Ni3P, at the Si chip solder joints. The results of this study suggest that co-bonding of active and passive components is possible through VR soldering for semiconductor packaging.

LED (Light Emitting Diode) lighting is gaining more and more market penetration as one of the global warming countermeasures. LED is the next generation of fusion source composed of epi/chip/packaging of semiconductor process technology and optical/information/communication technology. LED has been applied to the existing industry areas, for example, automobiles, TVs, smartphones, laptops, refrigerators and street lamps. Therefore, LED makers have been striving to achieve the leading position in the global competition through development of core source technologies even before the promotion and adoption of LED technology as the next generation growth engine with eco-friendly characteristics. However, there has been a point of view on the cost compared to conventional lighting as a large obstacle to market penetration of LED. Therefore, companies are developing a Chip-Scale Packaging (CSP) LED technology to improve performance and reduce manufacturing costs. In this study, we perform patent analysis associated with Flip-Chip CSP LED and flow chart for promising technology forecasting. Based on our analysis, we select key patents and key patent players to derive the business strategy for the business success of Flip-Chip CSP PKG LED products.