Earticle

Delta modulation plays a key role in data communication; the problem encountered in delta modulation is the slope over load error, which is inherent in the system. In order for the signal to have good fidelity, the slope-overload error needs to be as small as possible. Adaptive delta modulation reduces the slope over load error to a greater extent. ADM attempts to increase the dynamic range and the tracking capabilities of fixed step-size delta modulation. The adaptive algorithms adjust the step size (from a range of step sizes) to the power level of the signal and thus enhance the dynamic range of the coding system appreciably. This paper suggests a novel 1-bit Adaptive Delta Modulation technique for improving the signal-to-noise ratio (SNR) of Adaptive Delta Modulators (ADM). Various step-size algorithms are discussed and also their performance comparison is made. A new technique has also been discussed with a suitable pre-filer used for improving the SNR.

우리는 이 논문에서 ADPCM (adaptive differential pulse code modulation)을 적용함으로써 디밍 콘트롤러를 갖는 LED 드라이버의 설계를 제시한다. ADPCM 장비는 고해상도를 가지고 LED 전류를 정확하게 제어하며, 고조파 전류 펄스의 퍼짐으로 인하여 초래되는 RFI 를 감소시켜 준다. 또한 제어 동작의 정밀도를 높여준다. 이 연구에서 LED에 펄스 전류를 인가함으로써 고효율 에너지의 LED를 제어하는 디지털 제어회로의 설계를 제시한다. 우리가 설계한 LED 전류구동시스템은 디지털 제어 부와 아날로그 SMPS (스위치 모드 파워 서플라이)를 별도로 구현한 두개의 시스템이다. 입력레벨이 0.7 인 경우의 시뮬레이션 결과는 시그마 델타 변조를 하여 얻은 D/A 컨버터의 출력을 나타내었다. 개수가 510 개인 펄스신호의 경우 0.15 % 의 정밀도를 얻을 수 있었다.

In this paper, we present the LED dimming control system by using ADPCM (Adaptive Differential Pulse Code Modulation). This ADPCM apparatus accurately controls the LED current with high resolution reducing the RFI (radio frequency interference) due to the spreading out of the harmonics of current of pulses. Additionally, this makes it easier to increase the accuracy of control operation. This study introduces to make a digitally controlled circuit for controlling LED with high-energy efficient by adopting pulse current to LED. The LED current drive system we designed are two systems, the digitally-controlled unit and analog switching mode power supply unit, can be developed separately. The simulation shows the sigma delta modulation of digital to analog converter’s output when the input level is 0.7. From this simulation, the output is approached to accurately 0.15% to target value with 510 pulses.

This paper presents 3-phase current regulation of SR motor by only single current sensor. The conventional drive system of SR motor has a current sensor per each phase. In this paper, The asymmetric bridge converter which Is able to control independently phases and be excited simultaneously is used fs the driver system for 6/4 poles SR motor. And the sensor Is replaced 3 sensors of each phase with only one on bus line of converter so as to detect current of every phase. A drive logic circuit is designed on EPLD with Delta modulation using a fixed frequency This technique is verified through simulation and experiment.

In this paper, we have proposed a Parallel Resonant Soft Switching Inverter based on Delta-Modulation Method. The conventional full-bridge inverter generates switching losses due to the hard switching. The proposed inverter operates soft switching using a DC-link switch and resonant circuit. So, all of the switches in the proposed inverter operates soft switching. Therefore the proposed inverter can reduce not only switching loss but also capacity and size of passive devices due to the resonant elements. The validity of the proposed inverter is verified thorough the theoretical analysis and simulation.

A study is presented on the DDM (double delta modulation) system which incorporates another modulation loop in front of the delta modulation system. DDM is proposed to delta modulate the error signal which is derivated through the ordinary delta modulation. This system is constructed simply by adding a differential amplifier and an integrator to the basic DM system. Since signal-to-quantization noise ratio SNR is the most informative measure of quantizer performance, the formula of the max. SNR of the DDM system is derived and investigated experimentally for a sinusoidal input. The max. SNR of the DDM is larger than that of DM in low bit rate region and vice versa in high bit rate region.

The PWM (Pulse Width Modulation) control signals have a drawback in that their power spectrum tends to be concentrated around the switching frequency and the resulting harmonic spikes cause an EMI (Electromagnetic Interference) and switching losses in semiconductors, etc. The SDM (Sigma-Delta Modulation) is a type of switching modulation used to reduce these harmonic spikes, and several SDM schemes are investigated in this paper. In the DSDM (Dithered SDM), the SDSDM (Space-Dithered SDM) and TDSDM (Time-Dithered SDM), the signals are classified by the location of their random dither additions. In these schemes, the switching frequency is spread by a random dither generator placed on the input or the output parts. Experimental results are presented where the advantages of the new proposed CDSDM (Combined Dithered SDM) are confirmed by applying to a buck converter.

The delta modulation used for controlling the speed of an induction motor has high peak of harmonic spectrum at low speed range causing acoustic noises in the induction motor. This paper proposes to suppress the harmonics by synchronizing the reference signal with the hysteresis windows for controlling the distribution of the switching frequency. As a result we can decrease the peak of harmonic spectrum. The simulation results show that the peak spectrum of harmonics can be reduced up to 60%.

본 논문에서는 강압형 DC-DC 컨버터의 성능 개선을 위한 스위칭 기법인 2차 SDSDM (Space Dithered Sigma Delta Modulation)방식을 제안한다. PWM (Pulse Width Modulation) 방식은 일정 스위칭 주파수 대역에서의 고조파로 인해 소음, 전자파 장애, 스위칭 손실 등을 유발한다. 이러한 문제를 해결하기 위한 DSDM 방식의 일종인 1차 SDSDM은 랜덤 디더(Random Dither) 발생기가 1차 SDM의 양자화기(quatizer) 입력단에 위치하여 스위칭 주파수가 분산된다. 강압형 DC/DC 컨버터에 제안하는 2차 SDSDM의 방식을 적용한 실험 결과를 통해 타당성을 검증한다.

This paper proposes the 2nd-order SDSDM (Space Dithered Sigma-Delta Modulation) for performance improvement of a buck converter. The PWM (Pulse Width Modulation) has a drawback in that power spectrum tends to be concentrated around the switching frequency. The resulting harmonic spikes cause a EMI(Electromagnetic Interference) and switching loss in semiconductor, etc. The 1st-order SDSDM scheme is a kind of DSDM for reducing these harmonic spikes. In this scheme, a switching frequency is spread through random dither generator placed on input part. In experimental result, the proposed 2nd-order SDSDM is confirmed by applying to a buck converter.

본 논문에서는 강압형 DC-DC 컨버터의 성능 개선을 위한 스위칭 기법인 2차 SDSDM(Space Dithered Sigma-Delta Modulation)방식을 제안한다. PWM 방식은 일정 스위칭 주파수 대역에서의 고조파로 인해 소음, 전자파 장애, 스위칭 손실 등을 초래한다. 이러한 문제를 해결하기 위한 DSDM 방식의 일종인 1차 SDSDM은 랜덤 디더(Random Dither) 발생기가 1차 SDM의 양자화기(quatizer) 입력 단에 위치하여 스위칭 주파수가 분산된다. 강압형 DC/DC 컨버터에 제안하는 2차 SDSDM의 방식을 적용한 실험 결과를 통해 타당성을 검증한다.

A novel power amplifier for a polar transmitter is proposed to achieve better spectral performance for a wideband envelope signal. In the proposed scheme, 2-bit sigma-delta (${\Sigma}{\Delta}$) modulation of the envelope signal is introduced, and the power amplifier configuration is modified in a binary form to accommodate the 2-bit digitized envelope signals. The 2-bit ${\Sigma}{\Delta}$ modulator lowers the noise of the envelope signal by fine quantization and thus enhances the spectral property of the RF signal. The Ptolemy simulation results of the proposed structure show that the spectral noise is reduced by 10 dB in a full transmit band of the EDGE system. The dynamic range is also enhanced. Since the performance is improved without increasing the over-sampling ratio, this technique is best suited for wireless communication with high data rates.

The operation of a first-order 2-bit adaptive sigma-delta modulation system is described and discussed in this paper. The system operation is based on the combination of both "memory" and "look-ahead" estimation in the employed step-size adaptation algorithm of the basic quantizer. In comparison to simple systems and other adaptive sigma-delta systems, computer simulation results show that these features of the described system are responsible for the high SNR values and the extended dynamic range achieved for AC signals as well as the noise power reduction of almost 10 dB and the complete elimination of the idle tones for DC signals. However, such an advantageous performance requires the least possible multiplicative error accumulation, and this cannot be achieved without analog circuits of the highest possible accuracy.

The SDH (Synchronous Digital Hierarchy) has been rapidly acknowledged as a world wide transmission standard replacing the existing PDH infrastructure. A bit stuffing is used for synchronization between a PDH signal and a SDH node, and a pointer justification is used for synchronization between one SDH node and the other SDH node. During above processes - a bit stuffing and a pointer processing -, a stuffing jitter and a pointer Jitter are produced and the generated jitter can cause transmission error. In this study, a stuffing jitter and a pointer jitter are modeled and analyzed. A Sigma-Delta modulation is described and an advanced jitter reduction technique using a Sigma-Delta modulation technique in the Synchronizer, Pointer Processor and Desynchronizer is provided.

This paper presents a $0.13{\mu}m$ CMOS 3-level envelope delta-sigma modulation (EDSM) RF signal generator, which synthesizes a 2.6 GHz-centered fully symmetrical 3-level EDSM signal for high-efficiency power amplifier architectures. It consists of an I-Q phase modulator, a Class B wideband buffer, an up-conversion mixer, a D2S, and a Class AB wideband drive amplifier. To preserve fast phase transition in the 3-state envelope level, the wideband buffer has an RLC load and the driver amplifier uses a second-order BPF as its load to provide enough bandwidth. To achieve an accurate 3-state envelope level in the up-mixer output, the LO bias level is optimized. The I-Q phase modulator adopts a modified quadrature passive mixer topology and mitigates the I-Q crosstalk problem using a 50% duty cycle in LO clocks. The fabricated chip provides an average output power of -1.5 dBm and an error vector magnitude (EVM) of 3.89% for 3GPP LTE 64 QAM input signals with a channel bandwidth of 10/20 MHz, as well as consuming 60 mW for both channels from a 1.2 V/2.5 V supply voltage.

This paper presents a digital implementation of delta modulation Technique for Active Power Filters. Delta modulated scheme is to control the harmonic-compensating current indirectly by adjusting the capacitor voltage to be sinusoidal. The overall control system has two feedback loops. One is the outer propotional feedback for loop regulating the dc current of active filters and the other is the inner feedback loop for maintaining the ac current waveform to be sinusoidal, and have zero power factor angle(i.e. unity power factor). The characteristics of the proposed is investigated by digital simulation using ACSL and experimental results are obtained by TMS370C756 Single-Chip Microprocessor relative to analog delta modulation technique.

The problems of he plentiful harmonics and low power factor have occured to the increase of semiconductor power conversion equipments. These problems should be improved by the active power filters which have been studied recently. This paper described the appliaction of delta modulation technique to current-fed filter and control performance. Through digital simulation the output characteristics of delta modulator are investigated theoretically.

In the conventional current control methods for the current-type reactive power compensators, it is usual to compare the reactive reference current signal with the triangular wave and hence to generate the ON-OFF signals for the semiconductor reactive power compensator. To improve the response as well as the control capability, the delta modulated current control technique is proposed in this paper and studied theoretically.

Conducted electromagnetic interference (EMI) from switch mode power supplies (SMPS) has become a major problem due to the proliferation of these devices employing dc-dc converters using standard pulse width modulation (PWM). In this paper, we proposed the sigma-delta modulation $({\sum}{\Delta}M)$ as an alternative switching technique to reduce the conducted EMI in SMPS. A comparative investigation on conducted EMI generated by PWM and ${\sum}{\Delta}M$ techniques are experimentally performed on a 300W Boost converter.

This Paper presents Sigma-Delta Modulation(SDM) schemes to generate switching waveform for a high-power factor boost-type rectifier. The SDM scheme can be implemented by simple digital algorithm unlike conventional PWM schemes with several hardware, and has the characteristics of spectrum-spreading and noise-shaping effects, which are profitable in harmonic reduction of input current in the boost-type rectifier. The comparison results of their spectrum performances shows that the 1st-order SDM has better harmonic suppression effect than conventional PWM scheme and Dithered SDM scheme.