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2

Fabrication of CeO2 Buffer Layer Using MOD Process KCI 등재후보

Young-Kuk Kim, Jaimoo Yoo, Kookchae Chung, Jaewoong Ko

한국초전도저온학회 (구 한국초전도저온공학회) 한국초전도·저온논문지 (구 한국초전도저온공학회논문지) Vol.8 No.4 2006.12 pp.19-21

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3,000원

3

Effect of the thickness of CeO2 buffer layer on the YBCO coated conductor

Dongqi Shi, Ping Ma, Ho-Sup Kim, Hong-Soo Ha, Jun-Ki Chung, Kyu-Jeong Song, Rock-Kil Ko, Chan Park, Seung-Hyun Moon, Sang-Im Yoo

한국초전도저온학회 (구 한국초전도저온공학회) 한국초전도·저온논문지 (구 한국초전도저온공학회논문지) Vol.6 No.4 2004.11 pp.1-4

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4,000원

4

4,000원

CeO2 has been widely used for single buffer layer of coated conductor because of superior chemical and structural compatibility with ReBa2Cu3O7-δ(Re=Y, Nd, Sm, Gd, Dy, Ho, etc.). But, the surface of CeO2 layer showed cracks because of the large difference in thermal expansion coefficient between metal substrate and deposited CeO2 layer, when thickness of CeO2 layer exceeds 100 nm on the biaxially textured Ni-3%W substrate. The deposition rate has been limited to be less than 6 Å/sec in order to get a good epitaxy. In this research, we deposited CeO2 single buffer layers on biaxially textured Ni-3%W substrate with 2-step process such as thin nucleation layer(>10 nm) with low deposition rate(3 Å/sec) and thick homo epitaxial layer(>240 nm) with high deposition rate(30 Å/sec). Effect of deposition temperature on degree of texture development was tested. Thick homo epitaxial CeO2 layer with good texture without crack was obtained at 600 oC, which has Δφ value of 6.2 o, Δω value of 4.3 o and average surface roughness(Ra) of 7.2 nm within 10 ㎛ × 10 ㎛ area. This result shows the possibility of preparing advanced Ni substrate with simplified architecture of single CeO2 layer for low cost coated conductor.

 
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