Earticle

초록

영어

Resistive random-access memory (RRAM), one of the most potential candidates for synaptic devices, has been studied steadily for many years. However, destructive switching methods and process variations acted as factors that were difficult to apply to the neuromorphic system. In particular, the breakdown of switching layer may occur even before training is sufficiently performed if endurance is not secured in on-chip training. In this work, we propose a binary neural network of a hardware friendly learning algorithm to overcome this issue at system-level study. Binary neural network (BNN) can accelerate the time at which the recognition rate is saturated because all weight states are defined by one switching event. In addition, the resistance to variation can be improved by using the maximum/minimum of the current level of the memristors. However, the conventional BNN has the disadvantage that batch normalization and real value weights must be used together for learning. In this paper, we verified a method for learning BNN using boundary values.

목차

Abstract
I. INTRODUCTION
II. RESULTS AND DISCUSSION
III. CONCLUSION
ACKNOWLEDGMENT
REFERENCES

키워드

저자

• Yeongjin Hwang [ dept. Electronic Engineering Inha University ]
• Sangwook Youn [ dept. Electronic Engineering Inha University ]
• Hyungjin Kim [ dept. Electronic Engineering Inha University ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  한국차세대컴퓨팅학회 학술대회

• 간기

  반년간

• 수록기간

  2021~2025

• 십진분류

  KDC 566 DDC 004