Earticle

초록

영어

A-PHY interface, an automotive high-speed Serializer/Deserializer (SerDes) interface standard, was proposed by the mobile industry processor interface (MIPI). A-PHY interface created the retransmission (RTS) layer to ensure data transmission in noisy automotive environments. In this paper, we propose and design a detailed structure of the RTS layer of the A-PHY interface standard. The proposed RTS layer is designed to meet the A-PHY interface standard's retransmission specification and is implemented on the FPGA and verified by simulation and video data transmission. As a result of FPGA implementation, 2,019 registers, 3,924 LUTs, and 132 block memories were used, with a maximum operating frequency of 200 MHz.

목차

Abstract
I. INTRODUCTION
II. A-PHY AND RTS LAYER
A. A-PHY Architecture
B. A-Packet, A-PHY data transmission format
C. RTS Layer Architecture
III. EXPERIMENTAL RESULT
IV. CONCLUSION
REFERENCES

키워드

저자

• Sang-Ung Shin [ Department of Electric and Computer science Engineering Inha University ]
• Jin-Ku Kang [ Department of Electric and Computer science Engineering Inha University ]
• Yongwoo Kim [ Department of System Semiconductor Engineering Sangmyung University ] Corresponding Author

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  한국차세대컴퓨팅학회 학술대회

• 간기

  반년간

• 수록기간

  2021~2025

• 십진분류

  KDC 566 DDC 004