The 8th International Conference on Next Generation Computing 2022 (2022.10)바로가기
페이지
pp.207-209
저자
Taehwan Kim, Donghyun Kim, Hyunmin Shin, Saransh Rajjarwal, Gyungsu Byun
언어
영어(ENG)
URL
https://www.earticle.net/Article/A419776
원문정보
초록
영어
A 4Gb/s transceiver with the CTLE is presented. The proposed CTLE can recover the attenuated data up to 7dB by changing the digital codes which are received from the digital control logic. The proposed transceiver was designed and fabricated in 180-nm CMOS technology and consumes 60.37mW.
목차
Abstract I. INTRODUCTION II. TRANSCEIVER DESIGN A. Transmitter (TX) Design B. Receiver (RX) Design with CTLE C. Digital Logic for Digital Calibration IV. CONCLUSION REFERENCES