Earticle

초록

영어

In this paper, the method of controlling the clock that is inputted on the hardware from the application , and the hardware design method are to be proposed. When the hardware is synthesized to the Field Programmable Gate Array(FPGA), the input clock is fixed, and when the input clock is changed, the synthesis process must be passed again to require more time. To solve this problem, the Mixed-Mode Clock Manager(MMCM) module is mounted to control the MMCM module from the application. The controlled MMCM module controls the input clock of the module. The experiment was process the Neural Network algorithm in the x86 CPU and SIMT based processor mounted the FPGA. The results of the experiment, SIMT-based processors, the time that is processed at a frequency of 50MHz was 77ms, 100MHz was 34ms. There was no additional synthesis time due to a change of the clock frequency.

목차

Abstract
 1. Introduction
 2. Design of Hardware Loaded with Mixed-Mode Clock Manager Module and Application Program
  2.1 Mixed-Mode Clock Manager
  2.2 Hardware Design Method for Controlling Input Clock
  2.3 Input Clock Control in Application Program
 3. Experiments and Results
 4. Conclusion
 Acknowledgement
 References

키워드

저자

• Kwanho Lee [ Dept. Electronics and Computer Engineering, Seokyeong Univ. ]
• Jooyoung Lee [ Dept. Electronics and Computer Engineering, Seokyeong Univ. ] Corresponding author

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Advanced Culture Technology(IJACT)

• 간기

  계간

• pISSN

  2288-7202

• eISSN

  2288-7318

• 수록기간

  2013~2025

• 등재여부

  KCI 등재

• 십진분류

  KDC 600 DDC 700