Earticle

초록

영어

Low power consumption is gaining more significance for design of digital system design. The system has to be operated efficiently by consuming low power, which greatly increases the life of the battery. Every system has to be tested for its performance, before it is released into the market, hence testing is one of the major area of research. Testing of digital system is one of the main and important part in the design and implementation of digital integrated circuits. To ensure that the designed system responds properly, according to the system specification, testing is carried out. The quality of the chip produced will depend upon, how best the testing strategies, or the test vectors are chosen for testing the integrated circuit. The test patterns are generated with the help of automatic test pattern generators. Thus the performance of test pattern generator is very important. In this paper, a low power architecture for generating the test patterns, for testing digital integrated circuits is implemented. Verilog coding is done and is simulated using CADENCE simvision, and the RTL schematic is extracted. The gate level optimization is carried. The power consumed before optimization was found to be 166.79 mw, and the power consumed after optimization was found to be 65.88 mw. This paper presents the VLSI implementation low power test pattern generator. The performance parameters such as area, power and timing are also derived after the analysis.

목차

Abstract
 1. Introduction
 2. Literature Review
 3. Methodology
 4. Results and Discussions
 5. Conclusion
 References

키워드

저자

• Vardhana M [ I M.Tech. VLSI Design and Embedded Systems, NMAM Institute of Technology, Nitte, India ]
• Niju Rajan [ Assistant Professor, Department of Electronics and Communication Engineering, NMAM Institute of Technology, Nitte ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Hybrid Information Technology

• 간기

  격월간

• pISSN

  1738-9968

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605