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Implementation of Area and Power Efficient Pulse Shaping FIR Interpolation Filter for Multi Standard DUC
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- 발행기관
- 보안공학연구지원센터(IJSIP) 바로가기
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- 간행물
- International Journal of Signal Processing, Image Processing and Pattern Recognition 바로가기
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- 통권
- Vol.9 No.11 (2016.11)바로가기
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- 페이지
- pp.13-24
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- 저자
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- 언어
- 영어(ENG)
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- URL
- https://www.earticle.net/Article/A292852
※ 원문제공기관과의 협약기간이 종료되어 열람이 제한될 수 있습니다.
원문정보
초록
- 영어
- The multiplier occupies more area in the design of FIR filter, which is the basic element of any filter. The low complexity and power architecture of pulse shaping FIR filter for multi standard digital up converter was designed. In the existing system, a 2-bit binary common sub expression (BCS) elimination algorithm and shift and add method are used to design an efficient multiplier in the pulse shaping filter. In this paper, two different types of adders are used in accumulation unit of the filter to reduce power consumption and delay compared to the existing system. Adders plays vital role in Digital signal processing applications and also used in the digital integrated circuits. With the advances in technology, several researchers have contributed towards designing adders with either high speed, less power consumption, low area or the combination of them. In this Paper, we describes the analysis of speed, power and delay of two different types of adders like carry select adder and carry save adder for accumulation unit of root raised cosine (RRC) filter. The number of additions are reduced by using these adders and succeeded in reducing the delay, power and area. The designed pulse shaping FIR interpolation filter is simulated and synthesized using Xilinx tool for Spartan 3E family devices and simulation results are presented.
목차
Abstract
1. Introduction
2. The Reconfigurable Root Raised Cosine FIR Filter
2.1. Issues in Designing the Reconfigurable RRC FIR Filter for Multi Standard DUC
2.2. The BCSE Method for Solution
3. Methodology
3.1. Data Generator Block
3.2. Coefficient Generator Block
3.3. Coefficient Selector
3.4. Final Accumulation Unit
4. Results and Discussion
5. Comparison of Existing Method and Proposed Method
6. Conclusion
References
키워드
Digital up converter DUC Finite Impulse Response interpolation filter FIR interpolation filter Reconfigurable hardware architecture Software Defined Radio system SDR system저자
간행물 정보
발행기관
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- 발행기관명
- 보안공학연구지원센터(IJSIP) [Science & Engineering Research Support Center, Republic of Korea(IJSIP)]
- 설립연도
- 2006
- 분야
- 공학>컴퓨터학
- 소개
- 1. 보안공학에 대한 각종 조사 및 연구 2. 보안공학에 대한 응용기술 연구 및 발표 3. 보안공학에 관한 각종 학술 발표회 및 전시회 개최 4. 보안공학 기술의 상호 협조 및 정보교환 5. 보안공학에 관한 표준화 사업 및 규격의 제정 6. 보안공학에 관한 산학연 협동의 증진 7. 국제적 학술 교류 및 기술 협력 8. 보안공학에 관한 논문지 발간 9. 기타 본 회 목적 달성에 필요한 사업
간행물
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- 간행물명
- International Journal of Signal Processing, Image Processing and Pattern Recognition
- 간기
- 격월간
- pISSN
- 2005-4254
- 수록기간
- 2008~2016
- 십진분류
- KDC 505 DDC 605
이 권호 내 다른 논문 / International Journal of Signal Processing, Image Processing and Pattern Recognition Vol.9 No.11
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