Earticle

초록

영어

The latest mobile devices usually use multi-core technologies such as dual-core, quad-core or octa-core for high performance. Further, as the capacity of main memory in the mobile devices is growing, a lot of tasks are capable of running concurrently. With these trends, however, mobile devices run out of battery power faster than before. In recent years, next generation non-volatile memory technology (NVRAM) have developed significantly and considered as low-power main memory architecture. Traditionally, the bandwidth-aware multi-core task scheduling schemes have been studied in order to address the bandwidth saturation problem of shared main memory. In this paper, we propose a multi-core scheduling scheme considering DRAM/NVRAM hybrid main memory. The goal of the proposed scheme is to reduce the execution time of tasks by avoiding the memory bandwidth saturation as well as to improve the response time of interactive tasks. We have showed through trace-driven simulation that the proposed scheme outperforms the legacy scheduling schemes.

목차

Abstract
 1. Introduction
 2. Related Works
  2.1. Memory Bandwidth Aware Multi-Core Scheduling
  2.2. NVRAM Technology
 3. Proposed Scheme
  3.1. System Model
  3.2. Memory Bandwidth Calculation
 4. Experimental Results
 4. Conclusion
 References

키워드

저자

• Jeongmi Shin [ Department of Security and Management Engineering, Myongji University, Korea ]
• Yeonseung Ryu [ Department of Security and Management Engineering, Myongji University, Korea ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Control and Automation

• 간기

  월간

• pISSN

  2005-4297

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605