Earticle

초록

영어

To lower the mapping complexity of designing analog decoders, a method to optimize the design of low-density parity-check (LDPC) analog decoders is proposed in this paper. Based on factor graphs and the sum-product algorithm, the LDPC decoding process on the factor graph and the construction of analog decoders are exploited. Then the frequent subgraph mining algorithm is introduced to search the isomorphic subgraphs in factor graphs. According to the output of the frequent subgraph mining algorithm which enumerates all the subgraphs in factor graphs, the mapping complexity of a LDPC analog decoder can be significantly reduced. Finally, a (40, 16) LDPC analog decoder is constructed using the proposed method. Simulation results show that the need to place gates and connections can be reduced 90% and 23%, respectively, and the ideal performance is obtained by carefully choosing unit currents and decoding time.

목차

Abstract
 1. Introduction
 2. The Graphic Model of Analog Decoding over Memoryless Channels
 3. Frequent Subgraph Mining Algorithm
 4. Constructing the LDPC Analog Decoder with Kernel Blocks
  4.1. Simplification of Analog Decoder Mapping for CCSDS LDPC
  4.2. Structure of the Corresponding Analog Decoder
 5. The (40, 16) LDPC Analog Decoder and Simulation Results
  5.1. (40, 16) LDPC Analog Decoder and Mapping Complexity Analysis
  5.2. Simulation Results of the (40, 16) LDPC Analog Decoder
 6. Conclusion
 References

키워드

저자

• Yuan Gao [ School of Information and Electronics, Beijing Institute of Technology, Beijing, China ]
• Yujie Lin [ School of Information and Electronics, Beijing Institute of Technology, Beijing, China ]
• Jibo Dai [ School of Information and Electronics, Beijing Institute of Technology, Beijing, China ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Signal Processing, Image Processing and Pattern Recognition

• 간기

  격월간

• pISSN

  2005-4254

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605