High-speed Encryption & Decryption System Based on SM4 Algorithm
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- 발행기관
- 보안공학연구지원센터(IJSIA) 바로가기
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- 간행물
- International Journal of Security and Its Applications SCOPUS 바로가기
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- 통권
- Vol.10 No.9 (2016.09)바로가기
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- 페이지
- pp.1-8
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- 저자
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- 언어
- 영어(ENG)
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- URL
- https://www.earticle.net/Article/A284891
※ 원문제공기관과의 협약기간이 종료되어 열람이 제한될 수 있습니다.
원문정보
초록
- 영어
- Nowadays, the network transmission and video encryption areas have urgently needed high-speed encryption systems for SM4 algorithm. To speed up the SM4 system in small area, three aspects in existing system is analyzed and optimized. Firstly, aiming at the prior encryption must wait long until completing all 32 rounds key expansion, a method is proposed for outputting round key in each key expansion to accelerate encryption response. Secondly, considering most user passwords are unchanged, we adopt additional memory for comparing old and new keys, so that key expansion can be cancelled sometimes. Thirdly, the paper analyses the relationship between key expansion and encryption/decryption algorithm in SM4. Using module reused technology, the designed key expansion module can also encrypt and decrypt, and the designed another two modules can both encrypt and decrypt. Therefore, the system can achieve three tasks’ synchronous encryption/decryption, which greatly improves the system's processing speed. This paper presents a hardware design scheme for the high-speed system. At last, the optimized design is realized in FPGA. The experimental results show that the design is feasible, and the SM4 encryption speed can increase fourfold.
목차
Abstract
1. Introduction
2. SM4 Algorithm
3. Design Scheme for High-speed SM4 Encryption System
3.1. "Single cycle" in a Module and "Pipe Line" Inter Modules to Achieve a Small & High-Speed System
3.2. Memory and Comparator to Save Additional Key Expansion
3.3. Module Reuse to Run Three Encrypting / Decrypting Tasks Synchronously
4. Hardware Design for SM4 System
4.1. Design of Top-level Module
4.2. Design of Key-expansion/Encryption/Decryption Module
4.3. Design of Encryption/Decryption Module and Decryption/Encryption Module
4.4. Memory Design
4.5. Design of Control Module
5. Hardware Implementation based on FPGA
6. Conclusions
Acknowledgements
References
저자
간행물 정보
발행기관
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- 발행기관명
- 보안공학연구지원센터(IJSIA) [Science & Engineering Research Support Center, Republic of Korea(IJSIA)]
- 설립연도
- 2006
- 분야
- 공학>컴퓨터학
- 소개
- 1. 보안공학에 대한 각종 조사 및 연구 2. 보안공학에 대한 응용기술 연구 및 발표 3. 보안공학에 관한 각종 학술 발표회 및 전시회 개최 4. 보안공학 기술의 상호 협조 및 정보교환 5. 보안공학에 관한 표준화 사업 및 규격의 제정 6. 보안공학에 관한 산학연 협동의 증진 7. 국제적 학술 교류 및 기술 협력 8. 보안공학에 관한 논문지 발간 9. 기타 본 회 목적 달성에 필요한 사업
간행물
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- 간행물명
- International Journal of Security and Its Applications
- 간기
- 격월간
- pISSN
- 1738-9976
- 수록기간
- 2008~2016
- 등재여부
- SCOPUS
- 십진분류
- KDC 505 DDC 605
이 권호 내 다른 논문 / International Journal of Security and Its Applications Vol.10 No.9
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