Earticle

초록

영어

This paper proposes a pipelined scan driver architecture for a fingerprint sensor based on an integrator. The proposed pipelined scan driver secures enough time to integrate sensor signals of a fingerprint sensor because a fingerprint sensor based on an integrator requires a large number of clocks to get sensor signals of reasonable SNR. Therefore, the proposed pipelined scan driver reduces an overall image capture time effectively without performance degradation by integrating the sensor signals for several sensor cells simultaneously. A prototype 88x2 array fingerprint sensor combined with the proposed pipelined scan driver were designed in this paper. The implemented pipelined scan driver was simulated with Verilog HDL for the functional verification. The 88x2 fingerprint sensor with a synthesized pipelined scan driver were implemented and simulated using a standard 0.18μm CMOS technology. The simulation results were presented and analyzed in this paper.

목차

Abstract
 1. Introduction
 2. Fingerprint Sensor Cell Circuit
 3. Simulations
 4. Conclusion
 Acknowledgements
 References

키워드

저자

• Hyeopgoo Yeo [ Division of Information & Telecommunications, Hanshin University, Osan-Si, Korea ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Multimedia and Ubiquitous Engineering

• 간기

  월간

• pISSN

  1975-0080

• 수록기간

  2008~2016

• 등재여부

  SCOPUS

• 십진분류

  KDC 505 DDC 605