Earticle

초록

영어

Approximate computing is the theme that a system can let applications trade off accuracy for efficiency. It involves any technique where the system intentionally let on incorrectness to the application layer in order for conserving some resource. Floating point numbers i.e. approximate real number arithmetic to save space and time over arbitrary precession numerical representation. Approximate (APP) Computing is a technique of computation which ripostes less accuracy in results instead of an accurate output, which is enough for the desired application. The proposed work gives the basic allies on approximate computing based on arithmetic units using Verilog HDL. In dual mode operation, full adders and its types of adders resemble minimizing the power consumption and overall delay. Results show the great power saving efficiency and the 37mV and overall delay of 15.519ns.

목차

Abstract
 1. Introduction
 2. Design Implementation
  2.1. One bit DMFA Cell
  2.2. Eight-Bit Reconfigurable RCA Flat 
  2.3. Eight Bit Reconfigurable CLA (Carry Look Ahead Adder) Flat
 3. Experimental Results
 4. Conclusion
 References

키워드

저자

• Nithin Nagabasavanna [ M.Tech Scholar ]
• Nagaraju Chowdaiah [ Profressor, BGS Institute of Technology, Karnataka, India ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Hybrid Information Technology

• 간기

  격월간

• pISSN

  1738-9968

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605