Earticle

초록

영어

Adder circuits play an important role in reversible computation, which is helpful in diverse areas such as Low power CMOS design, quantum computing and nano technology. A reversible gate has equal number of inputs and outputs; so that, there should be one to one mapping between input and output vectors. Therefore, the input vector states can be always uniquely recovered from the output vector states. This paper presents a reversible residue circuit that requires only two reversible gates i.e. Modified TSG gate and Modified Fredkin Gate and consumes Low power. The design provides a significant reduction in the quantum cost of the circuit compared to the existing Residue Adder reversible logic implementation. For coding of design, VHDL language has been used. Xilinx design tool 14.4 and Xilinx project navigator tools are used for synthesis and simulation purpose.

목차

Abstract
 1. Introduction
 2. Terms Related to Reversible Logic Gates
  2.1. Quantum Cost
  2.2. Garbage Output
  2.3. Constant Inputs
  2.4. Gate Count
  2.5. Total Reversible Logic Implementation Cost (TRLIC) [4]
 3. Basic Reversible Logic Gates
  3.1. DPG Gate
  3.2. MTSG Gate
  3.3. MFRG Gate
 4. Proposed Work
 5. Simulation Results
 6. Conclusion
 References

키워드

저자

• Ankush [ M.Tech (Research Scholar) Department of ECE Punjabi University, Patiala, India ]
• Amandeep Singh Bhandari [ Assistant Professor Department of ECE Punjabi University, Patiala, India ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Hybrid Information Technology

• 간기

  격월간

• pISSN

  1738-9968

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605