Earticle

초록

영어

In VLSI design the reduction of power is an important criterion. The performance of a system mainly depends on the method of designing of various blocks of that system. To provide an efficient and meaningful architecture of a VLSI chip, a devoted design is needed which is power serviceable with less intricate. As computer systems have sequential circuit mostly, hence it is very necessary to design a sequential circuit which is more efficient and less power consuming. As different kind of counters are the important segments for different sequential circuits. Here, in paper we have proposed an efficient clock gating 4-bit Johnson counter using low power d flip flop. Power of d-flip flop is reduced by using power gating technique. By doing analysis in cadence at 180nm technology it is counted that our proposed design has lower power consumption i.e. power of the proposed design comes to be reduced by 40.3% which is 62.63e-6 and the reduced output is 37.4e-6. This is a great achievement in the VLSI industry than the conventional design, with a little enhancement of delay.

목차

Abstract
 1. Introduction
 2. Comparison between Low Power Techniques
 3. Low Power Design of D Flip-Flop
 4. Conventional Design of Johnson Counters
 5. Proposed Design of Johnson Counter Using Clock Gating Technique
 6. Simulations
 7. Results
 8. Advantages of Virtuoso Cadence
 Acknowledgments
 References

키워드

저자

• Sonia Sharma [ student (M.Tech. Vlsi Design), The Northcap University, Gurgaon, Haryana, India ]
• Neeraj Kr. Shukla [ student (M.Tech. Vlsi Design), The Northcap University, Gurgaon, Haryana, India ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Hybrid Information Technology

• 간기

  격월간

• pISSN

  1738-9968

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605