Earticle

초록

영어

Low power SRAM memory designs has become challenging for portable device applications. Semiconductor/ VLSI industry growth has exponentially demanding low leakage power SRAM designs for high performance chips and microprocessors. To get optimized standard cell memory design for battery operated devices at deep sub micron CMOS technology, a low leakage Asynchronous 8T SRAM is proposed. In this paper gated–ground P-P based low leakage 8T SRAM bit cell design is proposed for reducing the standby leakage power dissipation. The Proposed 8T SRAM bit - cell has used single bit line (single voltage source) for reading and writing operations to reduce active power consumption. The reduction of voltage swing and low standby leakage results appreciable reduction in total power consumption of the proposed design. The SPECTRE simulation and analysis at a 45nm CMOS feature size shows significant results in the proposed design at 0.7v supply voltage. Proposed Asynchronous single ended 8T SRAM bit - cell greatly reduced 99.92% stand by leakage power consumption and 11.76% of write ‘1’ active power consumption from the existing 8T SRAM bi – cell design. Whereas comparing with the standard 6T SRAM bit – cell design, proposed design also achieved 99.88% standby leakage power reduction and 95.8% of total active write ‘1’ power consumption from the conventional 6T SRAM bit – cell. This results overall total average power reduces in the proposed 8T SRAM bit-cell design i.e. reduction of 99.93% from the existing 8T SRAM bit – cell and 80.63% from the conventional 6T SRAM bit – cell design while keep maintaining the read static noise margin and write noise margin.

목차

Abstract
 1. Introduction
 2. Conventional 6T SRAM bit – cell design
 3. Existing 8T SRAM bit – cell design
 4. Proposed Asynchronous Single Ended 8T SRAM bit – cell
  4.1. Write Operation with Single Bit Line
  4.2. Read Operation with Single Bit Line
 5. Analysis and Simulation Work
  5.1. Operation Performance in the Proposed Design
  5.2. Leakage Power Dissipation
  5.3. Write ‘1’ Power Consumption
  5.4. Total Average Power Consumption
  5.5. Stability Analysis
 6. Conclusions
 7. Future Scope
 References

키워드

저자

• Sonam Jain [ PG Student, VLSI Design Group, Department of Electrical, Electronics & Communication Engineering, THE NORTHCAP University, Gurgaon (Haryana) India ]
• Neeraj Kr. Shukla [ Associate Professor, VLSI Design Group, Department of Electrical, Electronics & Communication Engineering, THE NORTHCAP University, Gurgaon (Haryana) India ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Hybrid Information Technology

• 간기

  격월간

• pISSN

  1738-9968

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605