Earticle

초록

영어

DRAM system has been more and more critical on modern multi-core architecture where the Moore’s law has been made effect on increasing the number of cores integrated in a processor chip. The performance of DRAM system is usually measured in term of bandwidth and latency, which are regarded as inherently depending on Row Buffer Hit Rate (RBHR) according to previous studies. In this paper, we find that Memory Level Parallelism (MLP) exhibits a stronger correlation with the performance of DRAM system on multi-core/many-core architecture than RBHR, and promoting MLP significantly improves DRAM system performance. In order to exploit the MLP, we have evaluated various approaches including multi-bank, multi-row-buffers, multi-memory-controllers and the obsolete Virtual Channel Memory (VCM). The experimental results show that VCM is a better alternative to traditional DRAM chip on multicore/many-core architecture than the other three approaches because VCM has almost all the advantages of the others: 1) it can improve homogeneous workloads’ IPC by 2.21X on a 16-core system with 32 virtual channels due to leveraging unexploited MLP. 2) It can also promote Quality-of-Service (QoS) of DRAM system by removing unfairness while memory controllers serve memory requests. 3) It can save energy and has low area costs. Unfortunately, VCM, which was proposed in the late 1990s, faded away before multi-core/manycore became dominated. Therefore, we suggest memory chip vendors reconsider the VCM technology for multi-core architecture.

목차

Abstract
 1. Introduction
 2. Background and Motivation
  2.1. DRAM Memory System
  2.2. MLP on Multi-Core Architecture
 3. Leveraging MLP
  3.1. VCM Organization
  3.2. VCM for Multicore Architecture
  3.3. Optimization for Contention and QoS
 4. Experimental Setup
  4.1. Evaluation Tools
  4.2. Workloads
  4.3. Metrics
  4.4. Experimental Schemes
 5. Experimental Results
  5.1. Performance
  5.2. Impact of VCM Parameters
  5.3. QoS
  5.4. Area and Power Cost
 6. Related Works
 7. Conclusion
 References

키워드

저자

• Yuxuan Wang [ Department of Computer, Shandong University, Weihai, China ]
• Yingping Zhang [ Hunan Electric Power Company, State Grid, China ]
• Xiaotian Zhang [ Department of Computer, Shandong University, Weihai, China ]
• Jian Yin [ Department of Computer, Shandong University, Weihai, China ]
• Licheng Chen [ Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Hybrid Information Technology

• 간기

  격월간

• pISSN

  1738-9968

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605