Earticle

초록

영어

In this paper, we illustrate a 0.4Tb/s full rate 2:1 MUX. In order to suppress the dilapidation of signals and to increase the operation speed, we designed interconnection for the circuit using self controllable voltage level (SVL) techniques. The circuit shows rise and fall times of about 100fs and consumes 0.5nW. The CMOS logic, such as SVL logic is renewed in this design. The designed circuit is realized in a standard 45nm process and uses 0.7V supply voltage. Our optimization technique using the proposed method reduces power consumption and leakage current by significant amount of multiplexer circuit. The same techniques and architectures are applicable for more advanced semiconductor technologies to push the speed even further.It is easy to tell that our 2:1 MUX attain the highest datarate 0.4Tb/s without increasing much power consumption as compared the data rate 50Gb/s and power to previous work.

목차

Abstract
 I. Introduction
 II. Conventional 2:1 MUX
 III. SVL Technique Applied in 2:1 MUX
  A. Upper SVL Circuit
  B. Lower SVL Circuit
  C. SVL Circuit
 IV. Simulation Result
 V. Conclusion
 References

키워드

저자

• Sanjay singh Kushwah [ ECED, GEC Gwalior, India ]
• SaritaBhadauria [ ECED, MITS, Gwalior, India ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Hybrid Information Technology

• 간기

  격월간

• pISSN

  1738-9968

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605