Earticle

초록

영어

This paper proposes an extended diagonal mesh (XDMesh) topology for network-on- chip (NoC) architectures to reduce latency and energy consumption for fast and low- power communication among remote nodes by including diagonal links in the network. In addition, we compare the performance of the proposed XDMesh with conventional state-of-the art topologies, including mesh, extended-butterfly fat tree (EFTI), and diametrical mesh, in terms of throughput, latency, energy consumption, and area overhead. Experimental results indicate that XDMesh outperforms the conventional topologies in terms of throughput and latency by varying the number of virtual channels and injection rate. Moreover, XDMesh achieves 46.28%, 35.29% and 19.37% lower energy consumption than EFTI, mesh, and diametrical mesh topologies, respectively, and 9.29%, 31.28%, and 15.23% lower silicon area, respectively.

목차

Abstract
 1. Introduction
 2. Background Information
  2.1. State-of-the-Art NoC Topologies
  2.2. Switching Strategies in NoC
  2.3. Research Motivations
 3. Proposed Topology and Routing Algorithm
  3.1. Proposed Topology
  3.2. The Proposed Routing Algorithm
 4. Experimental Results and Analysis
  4.1. Experimental Environment
  4.2. Analysis of Performance Results
  4.3. Analysis of Energy Consumption Results
 5. Conclusions
 Acknowledgements
 References

키워드

저자

• Md. Hasan Furhad [ Department of Electrical, Electronic and Computer Engineering, University of Ulsan, De 93 Daehak –ro, Nam-gu, Ulsan 680749, Korea ]
• Jong-Myon Kim [ Department of Electrical, Electronic and Computer Engineering, University of Ulsan, De 93 Daehak –ro, Nam-gu, Ulsan 680749, Korea ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Multimedia and Ubiquitous Engineering

• 간기

  월간

• pISSN

  1975-0080

• 수록기간

  2008~2016

• 등재여부

  SCOPUS

• 십진분류

  KDC 505 DDC 605