Earticle

초록

영어

In Digital systems like digital signal processors, FIR filters and micro processors etc, Multiplier is one of the key hardware blocks. The performance of the overall system is determined by the multiplier performance because the multiplier is generally the slowest element in the whole system and also it is occupying more area. In the multiplier, we use adder circuit repeatedly. So, an efficient adder circuit will be used in multipliers, it gives better performance. In the proposed work, new Carry Select Adders (CSLA) are replaced to enhance the multiplier performance. Carry Select Adder (CSLA) provides better performance with respect to speed and area. Previously, a binary to excess one converter (BEC) based Square Root Carry Select Adder is designed but in that data dependency is very high, it gives some speed penalty. An efficient CSLA design is obtained using improved logic units to eradicate the data dependency and redundant logic operations. In this proposed work, the intended efficient Square Root Carry Select Adder is compared with BEC based CSLA of respective architectures, after having comparison the proposed CSLA is efficient with respective to area and delay is used in Multiplier design. This work gives better results regarding to the performance parameters such as delay and area of designed multiplier using new efficient square root carry select adder compared to BEC based CSLA multiplier.

목차

Abstract
 1. Introduction
 2. Carry Select Adder
 3. BEC-Based CSLA
 4. New Logic Formulation of SQRT-CSLA
 5. MULTIPLIER DESIGN
 6. Performance Comparison of Multipliers using Synthesis Results
 7. Conclusion
 References

키워드

저자

• M Gopi [ GMR Institute of Technology ]
• GBSR Naidu [ Assistant Professor, GMR Institute of Technology ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Hybrid Information Technology

• 간기

  격월간

• pISSN

  1738-9968

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605