Earticle

초록

영어

This paper presents a novel optimal 2-D layout using PN and PNN pattern during placement, we utilize the device merging, abutment and alignment technique to enhance the wire-length and area-efficiency. A placement objective is formulated balancing the symmetry for routing and the area efficiency. To the best of my knowledge, this is the first piece of work that can handle PN and PNN pattern for placement and using device merging, abutment and alignment technique simultaneously. Two cell (MTIP3&IP3) are used to demonstrate the effectiveness of approach. Moreover, the proposed method generates more area-efficient transistor placements than the conventional method. In experiment we applied PN and PNN pattern for placement of devices with the device merging and abutment technique to attain the results for MTIP3 and IP3 cell 6.5025umsq and 3.114umsq respectively. Result shows that the area of IP3 cell is improved by 50%.

목차

Abstract
 1. Introduction
 2. Review of Related Work
 3. Description of the Problem
 4. The Approach
  4.1 Placement Techniques
 5. Experimental Results
 6. Conclusion and Future Scope
 References

키워드

저자

• Komal [ VLSI Design Group, ITM University, Gurgaon (Haryana) India ]
• Mohit Saxena [ Cadence Design Systems, Noida (Uttar Pradesh) India ]
• Shashank Chaturvedi [ Cadence Design Systems, Noida (Uttar Pradesh) India ]
• Neeraj Kr. Shukla [ VLSI Design Group, ITM University, Gurgaon (Haryana) India ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Advanced Science and Technology

• 간기

  월간

• pISSN

  2005-4238

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605