Earticle

초록

영어

TigerSHARC 201 link interface is a very efficient double data rate protocol. However, its inconsecutive characteristic of clock adds great difficulty for FPGA implementation when transmission rate is too high. In this paper, with specially-designed clock tree, ingenious rate decreasing strategy, plus proper control on FPGA place & routing processing, 8 group link transceivers with data rate over 500MB/s per lane were designed successfully on Xilinx Virtex6 XC6VLX130. Besides, no sophistic IOSERDES component was utilized. Whole design was completed via Verilog RTL code and Xilinx user constrained file. Presented design also has experienced harsh environment test, proved its efficiency and reliability.

목차

Abstract
 1. Introduction
 2. TS201 Link Protocol
 3. Link Transmitter Design
 4. Link Receiver Design
 5. Implementation Results
 6. Conclusion
 Acknowledgments
 References

키워드

저자

• Peng Wang [ College of Physics & Electronics, Xinyang Normal University, Xinyang, China, Communication ASIC Design Centre, Tongji University, Shanghai, China ]
• Ke Gong [ College of Physics & Electronics, Xinyang Normal University, Xinyang, China ]
• You-chao Tu [ College of Physics & Electronics, Xinyang Normal University, Xinyang, China ]
• Xiao-li Zhang [ College of Physics & Electronics, Xinyang Normal University, Xinyang, China ]
• Xin-wu Chen [ College of Physics & Electronics, Xinyang Normal University, Xinyang, China ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Security and Its Applications

• 간기

  격월간

• pISSN

  1738-9976

• 수록기간

  2008~2016

• 등재여부

  SCOPUS

• 십진분류

  KDC 505 DDC 605