Earticle

초록

영어

In this particular work, we have done power dissipation analysis of DES algorithm, implemented on 28nm FPGA. We have used Xilinx ISE software development kit for all the observation done in this particular research work. Here, we have taken SSTL (Stub-Series Terminated Logic) as input-output standard. We have considered six sub-categories of SSTL (i.e. SSTL135, SSTL135_R, SSTL15, SSTL15_R, SSTL18_I and SSTL18_II) for four different WLAN frequencies (i.e. 2.4GHz, 3.6GHz, 4.9GHz, and 5.9GHz). We have done analysis considering five basic powers i.e. clock power, logic power, signal power, IOs power, leakage power and total power. There is 50-60% reduction in power dissipation, which is possible with proper selection of the most energy efficient IO standards i.e. SSTL135_R among SSTL logic families.

목차

Abstract
 1. Introduction
 2. Related Work
 3. Power Analysis
  3.1. For Input-Output Standard :SSTL135
  3.2. For Input- Output Standard :SSTL135_R
  3.3. For Input- Output Standard :SSTL15
  3.4. For Input- Output Standard :SSTL15_R
  3.5. For Input-Output Standard :SSTL18_I
  3.6. For Input- Output Standard :SSTL18_II
 4. Comparison of Supply Power
 5. Conclusion
 6. Future Scope
 References

키워드

저자

• Bishwajeet Pandey [ Chitkara University Punjab ]
• Vandana Thind [ Chitkara University Punjab ]
• Simran Kaur Sandhu [ Chitkara University Punjab ]
• Tamanna Walia [ Chitkara University Punjab ]
• Sumit Sharma [ Chitkara University Punjab ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Security and Its Applications

• 간기

  격월간

• pISSN

  1738-9976

• 수록기간

  2008~2016

• 등재여부

  SCOPUS

• 십진분류

  KDC 505 DDC 605