Earticle

초록

영어

Design based upon CMOS logic are becoming increasingly attractive for many applications under electronic gadgets, but with increasing demand of small and portable devices, new techniques for low power are emerging. This paper focus on the design of subtarction logic for ALU sub-module in microprocessor design. Set of four different 10-T subtraction logic using Gate Diffusion Index(a new technique for low power design) has been designed using 180nm technology using Cadence Virtuoso and simulation are performed . Complete verification for performance of proposed subtraction logic is carried and circuit with least power and delay has been selected for the ALU design of the microprocessor. Layout design for the best optimum ciruit is designed using Layout XL and area of 17.28 X 11.135 um2 is calculated.

목차

Abstract
 1. Introduction
 2. Basic GDI Cell
 3. Implementation of Modules
 4. Result and Discussions
 5. Conclusion
 References

키워드

저자

• Haramardeep Singh [ Assistant Professor, LPU Jalandhar ]
• Harmeet Kaur [ Lecturer, BCET, Ludhiana ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Hybrid Information Technology

• 간기

  격월간

• pISSN

  1738-9968

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605