Earticle

초록

영어

In this paper we have aimed to have an energy efficient digital clock design. Digital clock is a type of clock that displays time digitally. The code has been implemented in Xilinx ISE Design Suite 14.2 and results were tested on 28nm FPGA platform using Kintex-7 FPGA family using different SSTL IOStandards. Comparison between different SSTL IOStandard has been done to achieve minimum IO power. Via SSTL technology, we achieve green computing with respect to low voltage impedance. In this work we are testing our digital clock design with different SSTL IOStandards such as SSTL15, SSTL18_II, SSTL135, SSTL12, SSTL18_I. In this work we have taken constant value of air flow and heat sink. Airflow has been kept 250 LFM and medium Heat sink. The design consists of five inputs and six outputs. At th end we concluded that there is 24-35% saving in total power dissipation with 1.2 GHz when compared with 2.2 GHz.

목차

Abstract
 1. Introduction
 2. Power Analysis
  A. Power Analysis for SSTL15 IO STANDARD
  B. Power Analysis for SSTL18_II IO STANDARD
  C. Power Analysis for SSTL135 IO STANDARD
  D. Power Analysis for SSTL12 IO STANDARD
  F. Power Analysis for different IO STANDARD with Different Frequencies
 3. Conclusion
 4. Future Scope
 References

키워드

저자

• Shivani Madhok [ Chitkara University, Chandigarh, Punjab ]
• Navdeep Singh [ Chitkara University, Chandigarh, Punjab ]
• Furqan Fazili [ Islamic University of Science & Technology, Awantipora, India ]
• Sumita Nagah [ Gyancity Research Lab, New Delhi, India ]
• Sweety Dabas [ Gyancity Research Lab, New Delhi, India ]
• Ravinder Kaur [ Department of Computer Science, Punjab University, Chandigarh, India ]
• Sweety Dabas [ Maharaja Surajmal Institute, Janakpuri, Delhi, India ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Control and Automation

• 간기

  월간

• pISSN

  2005-4297

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605