Earticle

초록

영어

In this paper, a new version of non-ideal model 08-bit current mode pipeline ADC has been developed. It is based on Matlab and Simulink environment with special focus given to the analog building blocks. Those blocks are current Sample-and-Hold(S/H), current Sub-ADC and current Sub-DAC. In this model, the sub-ADC is implemented by two current comparators and encoder logic circuit. For the current S/H and sub-DAC, they are implemented by using a switch current and current source. The main advantage of current mode approach is its low power dissipation, low cost and high speed. However, there are some technical limitations; using the model and running the simulation with the introduction of the main non idealities components such as a current offset, clock feed through, charge injection, clock jitter, switching noise, mismatch errors and non idealities in current amplifier, demonstrated clear degradation of the performance of the ADC.

목차

Abstract
 1. Introduction
 2. The Behavioral Model of CM 8 Bits Pipeline ADC
  2.1 1. 5 Sub-ADC Model
  2.2 1. 5 Sub-DAC Model
  2.3 Digital Block Structure
 3. Non Idealities Sources in CM Pipeline ADC
  3.1 Non Idealities in Current Sample and Hold
  3.2 Factors Non-ideal in Current Comparator
  3.3 Matching Errors in Current Sources
  3.4 The Non Idealities in Current Amplifier
 4. Simulation Results
 5. Conclusion
 References

키워드

저자

• Salah Hanfoug [ Advanced Electronics Laboratory (LEA), University of Batna, Avenue Chahid Boukhlouf, 05000, Batna, Algeria ]
• Fateh moulahcene [ Advanced Electronics Laboratory (LEA), University of Batna, Avenue Chahid Boukhlouf, 05000, Batna, Algeria ]
• Nour-Eddine Bouguechal [ Advanced Electronics Laboratory (LEA), University of Batna, Avenue Chahid Boukhlouf, 05000, Batna, Algeria ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Hybrid Information Technology

• 간기

  격월간

• pISSN

  1738-9968

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605