Earticle

초록

영어

A new Sliding Window Based Corner Detection Algorithm has been developed for image mosaicing. Using this algorithm, a new architecture suitable for VLSI implementation has also been designed. The proposed design incorporates a high degree of pipelining and parallelism and hence offers high throughputs. The color image mosaicing is achieved by first convolving an original image using a 3x3 sliding window followed by smoothening the image using median filters. The design has been coded in Verilog as per RTL coding guidelines. The algorithm has also been coded in Matlab in order to validate the hardware results. The Verilog design of the proposed architecture for image mosaicing has been implemented on Xilinx Spartan 6 xc6slx45-3fgg676 FPGA device. The design utilizes about 144,858 gates and the operating frequency is about 100 MHz. The design is capable of processing high resolution color pictures of sizes of up to 1600×1200 pixels in real time.

목차

Abstract
 1. Introduction
 2. Proposed Image Mosaicing Algorithm
  2.1 Design of ASM Chart
 3. Architecture of the Proposed Sliding Window Based Color Image Mosaicing System
  3.1 Architecture for Sliding Window Based Color Mosaicing System
  3.2 Sliding Window Architecture
  3.3 Convolution Module
  3.4 Corner Module
  3.5 Image Transformation Module
  3.6 Architecture of Multiplier
 4. Results and Discussions
  4.1 Place and Route Results
 5. Conclusion
 References

키워드

저자

• Jayalaxmi H [ Research Scholar JNTU, Hyderabad, India ]
• S. Ramachandran [ Research Scholar SJBIT, Bengaluru, India ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Signal Processing, Image Processing and Pattern Recognition

• 간기

  격월간

• pISSN

  2005-4254

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605