Earticle

초록

영어

This paper presents a VLSI implementation of reduced -complexity and reconfigurable MIMO(Multiple-Input Multiple-Output) signal detector targeting 3GPP-LTE standard. In recent wireless communication system, MIMO technology is considered as the key technique in LTE to meet the target. Maximum Likelihood (ML) detection is the optimal detection algorithm for MIMO systems. FPGA implementation of ML detector becomes infeasible as its complexity grows exponentially with the increase in number of antennas. Therefore, we propose a modified K-best detector algorithm which employs parallel and distributed sorting strategy combined with bitonic sorter that has near-ML detection solution. The design was implemented targeting Xilinx Spartan 6 device and the resource utilization results are presented and the performance comparison with the literature was also done. The total on-chip power estimated is 213mW.

목차

Abstract
 1. Introduction
 2. MIMO System Model
  2.1. Sphere Decoding Algorithm
 3. K-Best Algorithm
 4. Real –valued Decomposition
 5. Modified K-best Algorithm
 6. VLSI Architecture
  6.1. Bitonic Sorter
 7. Implementation and Results
 8. Conclusion
 References

키워드

저자

• Shirly Edward.A [ Department of ECE,SRM University, Vadapalani, Chennai, India ]
• Malarvizhi.S [ Department of ECE , SRM University, Kattankulathur, Chennai, India. ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Multimedia and Ubiquitous Engineering

• 간기

  월간

• pISSN

  1975-0080

• 수록기간

  2008~2016

• 등재여부

  SCOPUS

• 십진분류

  KDC 505 DDC 605