Earticle

초록

영어

Chip-multiprocessors have played a significant role in real parallel computer architecture design. For integrating tens of cores into a chip, designs tend towards with physically distributed last level caches. This naturally results in a Non-Uniform Cache Access design, where on-chip access latencies depend on the physical distances between requesting cores and home cores where the data is cached. Therefore, data movement and management impact access latency and power consumption. Remote misses limit the performance of multi-threaded applications, so using data locality is fundamental importance in Chip-multiprocessors. In this work we observed that a shared data writing behavior dramatically wastes precious on-chip cache resource and seriously affects the whole system performance. Therefore, we emphasis on improving the performance of applications that exhibit high data sharing, and propose a new prediction mechanism to predict accurately the impact of shared data and a scalable, efficient hybrid shared-aware cache coherence transition strategy which collaborate with directory-based MESI cache coherence protocol. In order to evaluate our proposal transition strategy, we experiment with the NAS Parallel Benchmarks and a modern Intel Harpertown multi-core machine. Results show the whole performance gains of up to 21% opposed to the traditional write-invalidate cache coherence transition strategy.

목차

Abstract
 1. Introduction
 2. Related Works
 3. Motivation and Background
  3.1. Motivation
  3.2. Write-invalidate Transition Strategy Vs Write-update Transition Strategy
 4. Hybrid Shared-aware Cache Coherence Transition Strategy
  4.1. Overview of the Transition Strategy
  4.2. Implementations
 5. Evaluation
  5.1. Methodology
  5.2. Results Analysis
 6. Conclusions
 Acknowledgments
 References

키워드

저자

• Sun Sun [ School of Computer Science and Technology University of Science and Technology of China No.96, Jinzhai Road, Hefei, Anhui, China ]
• Hong An [ School of Computer Science and Technology University of Science and Technology of China No.96, Jinzhai Road, Hefei, Anhui, China ]
• Junshi Chen [ School of Computer Science and Technology University of Science and Technology of China No.96, Jinzhai Road, Hefei, Anhui, China ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Hybrid Information Technology

• 간기

  격월간

• pISSN

  1738-9968

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605