Earticle

초록

영어

Nowadays, for providing the secure facilities and services to the user, the accurate identification is necessary. The Iris recognition is one of the attractive approach for user’s identification, provides high level of security and convenience then the other methods of identification like traditional ID and password, which can be lost or transferred. However, the iris recognition algorithms are implemented on general purpose sequential processing systems, such as generic central processing units (CPUs). Parallel processing is an alternative offers an opportunity to enhance the performance of system by increasing the speed. The most time consuming part of Iris recognition algorithm is matching part, which is implemented using Verilog HDL through ISE Design suit (14.2), achieved significantly reduction in execution time. The proposed design is suitable for integration either in ASIC or FPGA.

목차

Abstract
 1. Introduction
 2. Iris Segmentation
 3. Normalization
 4. Encoding
 5. Matching via Hamming Distance
 6. Conclusion
 Acknowledgements
 References

키워드

저자

• Tajinder pal Singh [ Lecturer of Chitkara University (India), tajinderpal.singh@chitkarauniversity.edu.in ]
• Sheifali gupta [ Associate Professor of Chitkara University (India) ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Signal Processing, Image Processing and Pattern Recognition

• 간기

  격월간

• pISSN

  2005-4254

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605