Earticle

초록

영어

This paper is investigated the low frequency noise behavior in subthreshold regime of gate-all-around silicon nanowire field effect transistors. Downscaling of multi gate structure beyond 50 nm gate length describes the quantum confinement related model. A drain current model has been described for output characteristics of silicon nanowire FET that is incorporated with velocity saturation effects and compact modeling of RF noise behavior is analyzed for gate-all-around structure. Noise performance of gate-all-around transistor is investigated at high frequency band for radio frequency RF specified application and consequently low frequency noise behavior can be analyzed using drain current model. This paper shows that noise is decreasing with frequency. Higher subthreshold, lower drain induced barrier lowering DIBL, higher on-off ratio and higher noise figure at lower frequency is achieved by gate all around configuration and comparison has been done with double gate structure.

목차

Abstract
 1. Introduction
 2. GAA Nanowire FET Design Concept And Simulation
  2.1. Drain Current Model
 3. Results and Analysis
  3.1. Subthreshold Regime
  3.2. Low Frequency Noise Simulation
 4. Conclusion
 Acknowledgements
 References

키워드

저자

• Awanit Sharma [ Department of Electronics, Jiwaji University, Gwalior, India ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Hybrid Information Technology

• 간기

  격월간

• pISSN

  1738-9968

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605