Earticle

초록

영어

A new sorting control system in field programmable gate array (FPGA) — the core of control — was proposed because the previous one couldn’t meet the requirements of the multi-channel and high yield. It focused on designs of both hardware circuit and FPGA programming module. In the system, the accurate lossless delay of multiple signals was applied by using of RAM and its control module in FPGA. The sorting signals were generated based on the parallel execution characteristics of FPGA program. Real-time communication was realized between CAN controller of SPI and human-computer interface. A large number of experiments were done to test the proposed system. Results showed that the sorting control system could process multi-channel and higher-yield signals significantly. And the materials sorter was improved both in detectable level and yield.

목차

Abstract
 1. Introduction
 2. System Design
  2.1. Hardware Circuit Design
  2.2. FPGA Programming Design
 3. Results
  3.1. The Simulation Diagram of Delay Signals
  3.2. The Simulation Diagram of Sorting Signals
  3.3. Experiment Platform
  3.4. Experiment Results
 4. Discussion
  4.1. Delay Signals
  4.2. Sorting Signals
  4.3. Experiment Result Analysis
 5. Conclusions
 Acknowledgments
 References

키워드

저자

• Ruihong Yu [ Department of Disaster Prevention Apparatus, Institute of Disaster Prevention East Yanjiao, Sanhe, Hebei, China, 065201 ]
• Jianxian Cai [ Department of Disaster Prevention Apparatus, Institute of Disaster Prevention East Yanjiao, Sanhe, Hebei, China, 065201 ]
• Hongrui Ma [ Department of Disaster Prevention Apparatus, Institute of Disaster Prevention East Yanjiao, Sanhe, Hebei, China, 065201 ]
• Yanqin Li [ Department of Disaster Prevention Apparatus, Institute of Disaster Prevention East Yanjiao, Sanhe, Hebei, China, 065201 ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Control and Automation

• 간기

  월간

• pISSN

  2005-4297

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605