Earticle

초록

영어

An new regular expression (regex) matching method based on Network-on-Chip(NoC) architecture is proposed in this paper. The idea is to combine a new kind of regex matching engine implemented in hardware with NoC architecture to get a high matching rate. The Regex matching was performed by partitioning the regex into several parts to make the finite state machine (FSM) simpler. Each part of regex can be matched by an engine cell core, and each core communicates with other cores by routers on a NOC topology. This method is suitable for different rule libraries in Deep packet inspection (DPI) and is easy to change the rule library of regex stored in memory. The engine was designed and implemented based on field programming gate array (FPGA) as a prototype and a model to implement the architecture in Application-Specific Integrated Circuits (ASIC) is also discussed in this paper. The experimental results show that this method can make regex matching much faster than traditional methods.

목차

Abstract
 1. Introduction
 2. Background
  2.1. Matching Algorithm based on DFA
  2.2. Matching Algorithm based on NFA
  2.3. Network on Chip
 3. Design of the Matching Engine
  3.1. Structure of the Matching Engine
  3.2. Performance of Matching Engine
 4. Experimental Results
 5. Conclusions
 Acknowledgements
 References

키워드

저자

• Cui Linhai [ Harbin University of Science and Technology, Harbin, China ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Smart Home

• 간기

  격월간

• pISSN

  1975-4094

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605