Earticle

초록

영어

A low power 5.8 GHz fully integrated CMOS low noise amplifier (LNA) with on chip spiral inductors for wireless applications is designed based on TSMC 0.18 μm technology in this paper. The cascode structure and power-constrained simultaneous noise and input matching technique are adopted to achieve low noise, low power and high gain characteristics. The proposed LNA exhibit a state of the art performance consuming only 6.4mW from a 1.8V power supply. The simulation results show that it has a noise figure (NF) only 0.972 dB, which is perfectly close to NFmin while maintaining the other performances. The proposed LNA also has an input 1-dB compression point (IP1dB) of -21.22 dBm, a power gain of 17.04 dB, and good input and output reflection coefficients, which indicate that the proposed LNA topology is very suitable for the implementation of narrowband LNAs in 802.11a wireless applications.

목차

Abstract
 1. Introduction
 2. Circuit Design and Analysis
  2.1. Topology
  2.2 Noise analysis
  2.3 The LNA circuit design
 3. Simulation Results and Discussions
 4. Conclusion
 Acknowledgements
 References

키워드

저자

• Mingcan Cen [ Department of College of Electronic Engineering, Guangxi Normal University ]
• Shuxiang Song [ Department of College of Electronic Engineering, Guangxi Normal University ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Hybrid Information Technology

• 간기

  격월간

• pISSN

  1738-9968

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605