Earticle

초록

영어

Systems have recently performed multiple functions through a combination of several IPs. SystemVerilog has useful components for modeling and verification at System-level. The OOP of SysemVerilog supports only single inheritance in a verification environment based on a layered testbench of SystemVerilog. It is restricted to construct environment verification. SystemC is a language for system level design at multiple abstraction levels and supports multiple inheritance. We adopt SystemC to design components of a verification platform which employ multiple inheritance, and combine it with the SystemVerilog-based verification platform using SystemVerilog DPI and the ModelSim macro in this paper. Employing the multiple inheritance of SystemC makes the design of a verification environment simple and easy through code reusability. Another characteristic of OOP with SystemVerilog and SystemC is that it can create a reconfigurable verification platform.

목차

Abstract
 1. Introduction
 2. Environment Using System Verilog & System C
  2.1. System Verilog-based Layered Test Bench
  2.2. Multiple Inheritance using OOP of System C
 3. Implement of System-Level Verification Environment
 4. Experimental Results
 5. Conclusions
 References

키워드

저자

• Young-Jin Oh [ Department of Electronics Enginneering, College of Electrical and Computer Engineering, Chungbuk National University, Cheongju,Chungbuk, 361-763, Korea ]
• Gi-Yong Song [ Department of Electronics Enginneering, College of Electrical and Computer Engineering, Chungbuk National University, Cheongju,Chungbuk, 361-763, Korea ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Control and Automation

• 간기

  월간

• pISSN

  2005-4297

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605