Earticle

초록

영어

The commonly used hardware verification languages, such as SystemVerilog have explicit coverage constructs which entitle verification engineers the power to model the function of design into coverage requirement. Verification Engineers usually subtract the functional coverage from their knowledge of the design requirements and map them into coverage points which can be expressed by hardware verification languages. However due to the limitation of syntax of these hardware verification languages, it is very hard in a reasonable way to specify the coverage points for the kind of module whose output is decided by scale-size relationship of its inputs. This paper presents a workaround to analyze the total effective scenarios for this kind of module. The paper also provides a method on how to model these effective scenarios with current syntax of hardware verification language.

목차

Abstract
 1. Introduction
 2. Method to Calculate Total Number of Scenarios
  2.1. Model the scenarios
  2.2. Recurrence derivation
  2.3. Original condition for recurrence derivation
  2.4. Calculation of an example with 6 inputs
 3. Method to Mark the Coverage Points
  3.1. Make a cross coverage based on each point’s possible position
  3.2. Exclude the unreasonable bins
  3.3 Coverage reports for an example with 6 inputs
 4. Related work and Conclusion
 Acknowledgements
 References

키워드

저자

• Lirong Qiu [ School of Information Engineering, Minzu University of China, Beijing, China ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Control and Automation

• 간기

  월간

• pISSN

  2005-4297

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605