Earticle

초록

영어

In this paper we describe the tunneling junction model effect on silicon nanowire gate-all-around field effect transistor using CMOS 45 nm technology. Tunneling effects provides better subthreshold slope, excellent drain induced barrier lowering and superior ION-IOFF ratio.This paper demonstrates the gate controlled tunneling at source of Gate-all-around field effect transistor. Low leakage current (off current) is reported of 2.9uA with considerable power reduction Subthreshold Swing SS is achieved of 46.5 mV/dec .Using Y function series resistance RSD is evaluated.Accurate evaluation of RSD of silicon nanowire Gate-all-around FET is shown linear behavior in inversion region using Y function. Silicon nanowire is considered as better aspect for ultra low power application.

목차

Abstract
 1. Introduction
 2. Design and Analysis of Tunneling Junction Model
 3. Analysis and Optimization of Series Resistance RSD
 4. Results and Analysis
 5. Conclusion
 Acknowledgements
 References

키워드

저자

• Awanit Sharma [ Reasearch Scholar of ITM Universe, Gwalior, India ]
• Shyam Akashe [ Associate Professor, Department of Electronics Instrumentation ITM University, Gwalior, India ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Advanced Science and Technology

• 간기

  월간

• pISSN

  2005-4238

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605