Efficient Design of Routing Node to Evaluate the Performance of Network Based Communication Infrastructure for SOC Design
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- 발행기관
- 보안공학연구지원센터(IJHIT) 바로가기
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- 간행물
- International Journal of Hybrid Information Technology 바로가기
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- 통권
- Vol.5 No.4 (2012.10)바로가기
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- 페이지
- pp.61-78
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- 저자
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- 언어
- 영어(ENG)
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- URL
- https://www.earticle.net/Article/A208226
※ 원문제공기관과의 협약기간이 종료되어 열람이 제한될 수 있습니다.
원문정보
초록
- 영어
- The current trend in technology has lead to the emergence of complex Systems-on-Chip (SoC). Traditionally, shared busses were used for communication between the different components in an SoC in which a communication link is shared between components in a time-division fashion, resulting in a communication latency. To overcome the limitations of common bus based design we have proposed Network-On-Chip based SoC architecture. The aim of this work is to present a modified architecture of the routing node to achieve higher area and power efficiency using changes at the RTL architecture level. FPGA implementation of 4x4 Router has been performed on Xilinx Spartan-3 FPGA XC3S400. ASIC implementation has been done using Design Compiler and IC compiler of SYNOPSYS with 90 nm SAED technology library. It was found that the proposed router has latency of 4 clock cycles, occupies 0.2 sq. mm of silicon area and operates at 500 Mhz frequency.
목차
Abstract
1. Introduction
1.1. Motivation for Network-on-chip based System-on-chip Architecture
1.2. Problem Statement
1.3. Proposed Design and Implementation Task
2. Literature Survey
2.1. Motivation for Router Design
2.2. Network -on- Chip
2.3. NoC Topologies
2.4. Switching Policy
3. Introduction to Generic Network on Chip Architecture
3.1. Routing Node
3.2. Input Blocks
4. Routing Node Simulation Results and FPGA Implementation
4.1. Simulation Results of a 4 x 4 Routing Node
4.2. FPGA Implementation of Routing Node
4.3. Testing Scheme for FPGA
4.4. The Hardware Setup to Implement the 4x4 Router
4.5. ASIC Implementation of Routing Node
5. Conclusion and Future Work
References
키워드
AHB ASIC NoC NI (network interface) PE (processing element) SoC저자
간행물 정보
발행기관
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- 발행기관명
- 보안공학연구지원센터(IJHIT) [Science & Engineering Research Support Center, Republic of Korea(IJHIT)]
- 설립연도
- 2006
- 분야
- 공학>컴퓨터학
- 소개
- 1. 보안공학에 대한 각종 조사 및 연구 2. 보안공학에 대한 응용기술 연구 및 발표 3. 보안공학에 관한 각종 학술 발표회 및 전시회 개최 4. 보안공학 기술의 상호 협조 및 정보교환 5. 보안공학에 관한 표준화 사업 및 규격의 제정 6. 보안공학에 관한 산학연 협동의 증진 7. 국제적 학술 교류 및 기술 협력 8. 보안공학에 관한 논문지 발간 9. 기타 본 회 목적 달성에 필요한 사업
간행물
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- 간행물명
- International Journal of Hybrid Information Technology
- 간기
- 격월간
- pISSN
- 1738-9968
- 수록기간
- 2008~2016
- 십진분류
- KDC 505 DDC 605
이 권호 내 다른 논문 / International Journal of Hybrid Information Technology Vol.5 No.4
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