Earticle

초록

영어

Hardware implementations of finite field arithmetic using normal basis are advantageous due to the fact that the squaring operation can be done at almost no cost. In this paper, a new word-parallel bit-serial finite field multiplier using normal basis is presented. The proposed architecture takes w clock cycles to compute the product bits, where the value for w, 1≤w≤m, can be arbitrarily selected by the designer to set the trade-off between area and speed. It has been shown that the proposed architecture has significantly lower complexity and critical path delay in comparison to the previously proposed architectures.

목차

Abstract
 1. Introduction
 2. The Bit-Serial Normal Basis Multiplier over GF(2m)
 3. The word-parallel bit-serial normal basis multiplier
 4. Conclusion
 Acknowledgements
 References

키워드

저자

• Yong Suk Cho [ Department of Information & Communication Security, Youngdong University ]
• Jae Yeon Choi [ Department of Information & Communication, Namseoul University ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Control and Automation

• 간기

  월간

• pISSN

  2005-4297

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605