Earticle

초록

영어

As integration densities continue to increase, interconnection has become one of the most important factors in determining the performance of multi-core processors. Recently, in order to reduce the delay due to interconnection, many studies have focused on the 3D multi-core processors. Compared to 2D multi-core architecture, 3D multi-core architecture gets decreased interconnection delay and lower power consumption owing to reduced wire length. Despite the benefits mentioned above, 3D design cannot be practical because it causes serious thermal problems in multi-core processors due to high power density. In this paper, we analyze temperature behavior of 3D multi-core processors according to various placement of core and level-2 cache. According to our simulation results, the floorplan where the core is stacked adjacently to the level-2 cache can reduce the temperature by 22% with 4-layers, and by 13% with 2-layers on the average, compared to the floorplan where the core is stacked adjacently to the core.

목차

Abstract
 1. Introduction
 2. Floorplan Schemes
 3. Experiments
 4. Conclusion
 Acknowledgements
 References

키워드

저자

• Dong Oh Son [ School of Electronics and Computer Engineering, Chonnam National University ]
• Hong Jun Choi [ School of Electronics and Computer Engineering, Chonnam National University ]
• Hyung Gyu Jeon [ School of Electronics and Computer Engineering, Chonnam National University ]
• Cheol Hong Kim [ School of Electronics and Computer Engineering, Chonnam National University ] Corresponding Author

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Control and Automation

• 간기

  월간

• pISSN

  2005-4297

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605