Earticle

초록

영어

Current Floating-point divisor architectures have low frequency, larger area and high latency in nature. With advent of more graphic, scientific and medical applications, floating point dividers have become indispensable and increasingly important. However, most of these modern applications need higher frequency or low latency of operations with minimal area occupancy. In this work, highly optimized pipelined architecture of an IEEE-754 standard double precision floating point divider is designed to achieve high frequency on FPGAs. By using secondary clock to perform mantissa division the overall latency of the divisor is reduced to 30 clock cycles, i.e. 52% less compared to conventional divisors. This design is mapped onto a Virtex-6 FPGA and an operating frequency of 452.69 MHz is achieved. The proposed design also handles all the IEEE specified four rounding modes, overflow, underflow and various exception conditions.

목차

Abstract
 1. Introduction
 2. Double Precision Floating Point Divider Based on IEEE-754 Binary Floating Point Standard
 3. Proposed Architecture
  3.1. Base Architecture for Divider
  3.2. Reducing the Latency using Secondary Clock
  3.3 Increasing the Frequency of Divider using Pipelining
 4. Results
 5. Conclusion
 References

키워드

저자

• Purna Ramesh Addanki [ Department of ECE, Sri Vasavi Engineering College, Pedatadepalli, Tadepalligudem, India ]
• Venkata Nagaratna Tilak Alapati [ Professor of ECE, V.R.Siddhartha Engineering College, Kanuru, Vijayawada, India ]
• Mallikarjuna Prasad Avana [ Professor of ECE, JNTUK, Kakinada, India ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Advanced Science and Technology

• 간기

  월간

• pISSN

  2005-4238

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605