Earticle

초록

영어

This paper presents Adaptive methodology to compensate the On Chip Variations (OCV), aging effect and manufacturing uncertainties in sub threshold circuits. “Canary flip-flop (FF),” is used to predict the timing violations. A FSM, 4-bit Counter, in CMOS 90nm technology whose performance is controlled by automatically changing voltage levels (DVS) as per the timing error prediction. In addition, the voltage supply is further scaled down if no timing error is predicted within certain time period to save more power at different PVT conditions. Back end simulation results shows, the design under observation with this technique can compensate process, supply voltage and temperature instability with an efficient power savings of nearly 40% with respect to the conventional worst case design with timing margins approach. Here we also demonstrate how to define the delay of delay chain during the design phase itself.

목차

Abstract
 1. Introduction
 2. Auto-Adaptive Speed and Power Control
  2.1. Overview
  2.2. Block Level Architecture
 3. Implementation
  3.1 Flow, Tools and Technology
  3.2 Overview
  3.3. Canary/Shadow Flip-Flop Implementation
  3.4. Delay Chain Implementation
  3.5 Adaptive Technique Implementation
 4. Measurements and Results
  4.1. Delay chain Calibration
  4.2 Adaptive Compensation of Voltage with DVS
  4.3 Ramping Up the Active Power Supply
  4.4 Ramping Down the Active Power
 5. Conclusion
 6. Future Scope
 References

키워드

저자

• Jasmer Singh [ STMicroelectronics Pvt. Ltd, Greater Noida, Uttar Pradesh, India ]
• Saha K [ STMicroelectronics Pvt. Ltd, Greater Noida, Uttar Pradesh, India ]
• GL Pahuja [ N. I. T. Kurukshetra, Kurukshetra, Haryana, India ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Advanced Science and Technology

• 간기

  월간

• pISSN

  2005-4238

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605